Three-step converter

An A/D converter comprising:

• upper comparison voltage generating means for dividing a reference voltage into a plurality of large-level regions with first voltage-dividing elements and outputting voltages at boundaries of the individual large-level regions as upper comparison voltages;
• a plurality of upper comparators comparing an analog input voltage with said upper comparison voltages;
• upper determining means for determining, from output signals of said upper comparators, to which one of said large-level regions said analog input voltage belongs, wherein said determining means includes first converting means for outputting a predetermined upper digital code in accordance with said determined large-level region;
• middle comparison voltage generating means for dividing said large-level region to which the analog input voltage is determined to belong by said upper determining means, into a plurality of middle-level regions with second voltage-dividing elements and outputting voltages at boundaries of said middle-level regions as middle comparison voltages, the second voltage-dividing elements being commonly used with the first voltage-dividing elements;
• a plurality of middle comparators comparing said analog input voltage with said middle comparison voltages;
• middle determining means for determining, from output signals of said middle comparators, to which one of said middle-level regions said analog input voltage belongs, wherein said determining means includes second converting means for outputting a predetermined middle digital code corresponding to said determined middle-level region;
• lower comparison voltage generating means for dividing said middle-level region to which the analog input voltage is determined to belong by said middle determining means, into a plurality of small-level regions with third voltage-dividing elements and outputting voltages at boundaries of said small-level regions as lower comparison voltages;
• switching means for selectively connecting the lower comparison voltage generating means in parallel to the determined middle-level region by the middle determining means;
• a plurality of lower comparators comparing said analog input voltage with said lower comparison voltages;
• and
• lower determining means for determining, from output signals of said lower comparators, to which one of said small-level regions said analog input voltage belongs, wherein said determining means further includes a converting means for outputting a predetermined lower digital code in accordance with said determined small-level region, wherein
• said third voltage-dividing elements including one of a capacitor string comprising a plurality of series-connected capacitors and a resistor string comprising a plurality of series-connected resistors, each resistor of the resistor string having a high resistance sufficient to avoid influencing the determined regions of the second voltage-dividing elements.