Low voltage CMOS process and device with individually adjustable LDD spacers

An integrated circuit comprising:

• at least one n-channel transistor having a gate, a source and a drain;
• at least one p-channel transistor having a gate, a source and a drain;
• at least one spacer located adjacent the gate of said n-channel transistor;
• and
• at least one additional spacer located adjacent the gate of said p-channel transistor, said at least one additional spacer being different in size than the at least one spacer of said n-channel transistor. a relative size of said at least one spacer and said at least one additional spacer being selected to provide balanced operation of said n-channel transistor and said p-channel transistor in response to a variation in voltage of a voltage power source of said n-channel and p-channel transistors, wherein said at least one spacer has a height substantially equal to said n-channel transistor gate and said at least one additional spacer has a height substantially equal to said p-channel transistor gate.

An integrated circuit comprising:

• at least one n-channel transistor having a gate, a source and a drain;
• at least one p-channel transistor having a gate, a source and a drain;
• at least one spacer located adjacent the gate of said n-channel transistor;
• and
• at least one additional spacer located adjacent the gate of said p-channel transistor, said at least one additional spacer being different in size than the at least one spacer of said n-channel transistor, a relative size of said at least one spacer and said at least one additional spacer being selected to provide balanced operation of said n-channel transistor and said p-channel transistor in response to a variation in voltage of a voltage power source of said n-channel and p-channel transistors when said voltage power source is varied over a range of at least 3 volts to 5 volts, wherein said at least one additional spacer has a height substantially equal to a height of said at least one spacer.

An integrated circuit comprising:

• at least one n-channel transistor having a gate, a source and a drain;
• at least one p-channel transistor having a gate, a source and a drain;
• at least one spacer located adjacent the gate of said n-channel transistor;
• and
• at least one additional spacer located adjacent the gate of said p-channel transistor, said at least one additional spacer being different in size than the at least one spacer of said n-channel transistor, a relative size of said at least one spacer and said at least one additional spacer being selected to provide balanced operation of said n-channel transistor and said p-channel transistor in response to a variation in voltage of a voltage power source of said n-channel and p-channel transistors when said voltage power source is varied over a range of at least 3 volts to 5 volts, wherein said at least one spacer has a height substantially equal to said n-channel transistor gate and said at least one additional spacer has a height substantially equal to said p-channel transistor gate.