Plug structure and process for forming stacked contacts and metal contacts on static random access memory thin film transistors

A novel plug structure for stacked contacts and metal contacts on a Static Random Access Memory (SRAM) cell having thin film transistors, on a partially completed semiconductor substrate having device areas and field oxide areas and further having field effect transistors (FETs) and word lines formed from a first polysilicon layer and Vss ground plate formed from a second polysilicon layer comprising of:

• a first insulating layer on said substrate;
• a patterned N+ doped third polysilicon layer on said first insulating layer forming first and second gate electrodes for a first and second thin film transistor;
• a second insulating layer forming a gate oxide on said first and second gate electrodes;
• a patterned N type amorphous silicon layer on said second insulating layer with P+ doped areas over said first and second gate electrodes and with undoped P+ type areas for channel regions on said first and second thin film transistors;
• and
• said channel regions contiguous with said P-doped areas and said P-doped areas extending over areas of the other said gate electrode and on said second insulating layer;
• said patterned N type amorphous silicon layer having openings in said P-doped areas of said amorphous polysilicon layer over said other gate electrode area and to said second insulating layer;
• a third insulating layer over said patterned N type amorphous silicon layer having openings aligned over and larger in size than said openings in said P doped portions of said amorphous silicon layer,
• said third insulating layer openings extending to said amorphous layer and further to said third polysilicon layer, and said third insulating layer having other openings to device areas elsewhere on said substrate;
• conducting plugs in said third insulating layer openings and thereby having low resistance ohmic stacked contacts for said thin film transistors and other conducting plugs in said other openings elsewhere to device areas on said substrate;
• a patterned first metal layer forming electrical interconnections, and thereby having said novel plug structure on said SRAM cell.