Method of fabricating an integrated circuit having punch-through suppression

A method of fabricating an integrated circuit having punch-through suppression between two regions of a device, the device including a channel region between the two regions, the method comprising the steps of:

• providing a semiconductor substrate;
• implanting a punch-through dopant at least between the two regions of the device to form a punch-through dopant implant;
• forming a gate on the substrate over the channel region;
• and
• implanting an implant material through the gate wherein the implant material accumulates below the channel region, wherein at least a portion of the punch-through dopant is below the implant material;
• whereby the accumulation of implant material suppresses punch-through between the two regions of the device and further suppresses diffusion of the punch-through dopant implant upward into the channel region.

A method of fabricating an integrated circuit having electrical isolation between two regions of the integrated circuit, the method comprising the steps of:

• providing a semiconductor substrate;
• implanting a punch-through dopant between the two regions of the device to form a punch-through dopant implant;
• forming a conductive structure on the substrate;
• and
• implanting inert ions through the conductive structure and through the two regions of the device wherein the inert ions form a first accumulation at least a portion of which is below the conductive structure and extending at least the width of the conductive structure and second and third accumulations below the two regions of the device wherein at least a portion of the punch-through dopant is below the first accumulation;
• whereby the accumulations of inert ions provide electrical isolation of the two regions of the device.