Universal serial bus (USB) RAM architecture for use with microcomputers via an interface optimized for integrated services device network (ISDN)

A RAM-based interrupt-driven serial interface device for establishing a communication link between a high performance serial bus host and a microcontroller device providing a control function, the interface device being operative to receive digital information in the form of information packets from the host and to process the packets and store the processed digital information in RAM memory buffers, then to generate an interrupt signal to the microcontroller device, and in response thereto, the microcontroller device being operative to access digital information stored in particular locations in the RAM memory buffers, and in response to said information, to write other information into other locations in the RAM memory buffers, then generate an interrupt signal to the interface device, which then interprets said other information, comprising:

• timing and control means for controlling storage of data buffer descriptor information describing the particular RAM memory buffers;
• dual port RAM means including data storage buffers, a descriptor storage buffer and means for permitting independent access to said descriptor storage buffer by both the microcontroller device and the serial interface device;
• means by which the microcontroller device can signal said timing and control means that said descriptor storage buffer has been initialized;
• hardware based storage means for storing descriptor information describing particular locations in said data storage buffers, such information to be used dynamically while transferring data to and from the high-performance serial bus and the data storage buffers described by the data buffer descriptor information, said timing and control means and said dual port RAM means being further operative to access said descriptor storage buffer and to copy the descriptor contents into said hardware based storage means, and being further operative to manage said data transfer between the data storage buffers and the serial bus;
• means for generating interrupt signals for signaling the microcontroller device upon completion of the data transfer between the serial bus and the data storage buffer described by said descriptor contents;
• means for receiving address information and read and write strobes from the microcontroller device for accessing the described data storage buffer so that data can be exchanged between the dual port RAM means and the microcontroller device;
• means for inhibiting storage of serial transfers from the host after an interrupt signal is sent to the microcontroller device thereby allowing the microcontroller to access uncorrupted data from the described data storage buffer;
• means for receiving an interrupt signal from said microcontroller device signaling that access to the data storage buffer has been completed and that a data storage buffer described by the descriptor contents is available for use;
• means for disabling said inhibit means so that additional data transfer between the high performance serial bus and the data storage buffer can occur;
• means for detecting errors occurring during data transfers and for reinitializing said descriptor storage buffer for use in a “re-try” attempt;
• and
• means for indicating that an error has occurred during data transfers and for signaling the host via the high performance serial bus that a “re-try” is required.