System and method for erasing non-volatile memory cells
AssigneeAMIC Technology Corporation
InventorsKou-Su Chen, Shih-Chun Fu, Jui-Te Chan
Life of this patent
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Abstract
A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
Claims17
A method of erasing flash memory cells in a flash memory cell array, the method including the steps of:
- (a) modifying electrical charge on floating gates of the flash memory cells by applying a partial erase signal having a magnitude and duration configured to affect substantially less electrical charge on said floating gates than that electrical charge required to place such memory cells into a fully erased state;
- and
- (b) repeating step (a) for a first number of pulses n so as to substantially equalize electrical field intensities across tunnel oxides associated with said floating gates of the flash memory cells;
- (c) performing an erase operation by applying an erase signal for a second number of pulses N (where N>>n) to place such cells in said fully erased state.
A method of erasing flash memory cells in a flash memory cell array, the method including the steps of:
- (a) modifying electrical charge on floating gates of the flash memory cells while they are in a non-erased state by applying a partial erase signal adapted to be substantially lower in intensity than a full strength erase signal;
- and
- (b) repeating step (a) if necessary for a first number of pulses n to substantially reduce threshold voltages of all of the flash memory cells to be below a target threshold voltage value;
- (c) applying an erase signal to such flash cells, which erase signal is adapted to place such cells in a fully erased state, for a second number of pulses N, where N>>n,;
- (d) determining whether such flash cells are actually in said fully erased state;
- and
- (e) if such flash cells are not in a fully erased state, performing a convergence cycle on the flash cells to adjust said threshold voltages to a fully erased state.
A system for erasing flash memory cells comprising:
- (a) a pre-erase controller circuit for controlling a flash cell pre-erase signal to be applied to the flash cells, said flash cell pre-erase signal being configured to remove a quantity of charge from the flash cells that is related to an erase speed of the flash cell and further being insufficient to place such flash cells into an erased state;
- and
- (b) an erase controller circuit for controlling a flash cell erase signal to be applied to the flash cells, said flash erase signal being adapted to place such flash cells into an erased state.
Dependencies are inferred from the claim text.