Biasing scheme for GAASFET amplifier
AssigneeSigem Inc.
InventorGyles Panther
Life of this patent
Estimating the term…
Abstract
A bias circuit for a pair of field effect transistor (FET) stages comprising a circuit for AC coupling a signal amplified by a first stage to the input of a second stage, a power source for supplying DC operating current to both of the stages in series, a circuit for sensing current drawn by the second stage and in response thereto for controlling bias of the first stage, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit.
Claims21
A bias circuit for a pair of field effect transistor (FET) stages comprising a circuit for AC coupling a signal amplified by a first stage to the input of a second stage, a power source for supplying DC operating current to both of the stages in series, a circuit for sensing operating current drawn by the second stage and in response thereto for controlling bias of the first stage, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit, including a circuit for comparing a voltage derived from the sensed current with a bandgap voltage and for raising or reducing bias as a result of any difference therebetween.
A bias circuit for a pair of field effect transistor (FET) stages comprising a circuit for AC coupling a signal amplified by a first stage to the input of a second stage, a power source for supplying DC operating current to both of the stages in series, a circuit for sensing operating current drawn by the second stage and in response thereto for controlling bias of the first stage, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit, including a charge pump controlling circuit for controlling a charge pump from said sensed current, and for controlling said bias by the charge pump.
A bias circuit for a pair of field effect transistor (FET) stages comprising a circuit for AC coupling a signal amplified by a first stage to the input of a second stage, a power source for supplying DC operating current to both of the stages in series, a circuit for sensing operating current drawn by the second stage and in response thereto for controlling bias of the first stage, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit, including a comparing circuit for comparing a voltage derived from the sensed current with a bandgap voltage, a charge pump controlling circuit for controlling a charge pump as a result of any difference therebetween, and for controlling said bias by the charge pump.
A bias circuit for a pair of field effect transistor (FET) stages comprising a circuit for AC coupling a signal amplified by a first stage to the input of a second stage, a power source for supplying DC operating current to both of the stages in series, a circuit for sensing operating current drawn by the second stage and in response thereto for controlling bias of the first stage, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit, and in which the first and second stages are comprised of respective first and second FETs, the power source having one polarity node coupled to the drain of the second FET and having an opposite polarity node coupled to the source of the first FET, the circuit for sensing being comprised of a resistor which is DC coupled between the source-drain circuit of the second FET and the drain-source circuit of the first FET and a circuit for detecting a voltage drop across the resistor and for controlling bias of the first FET, and further including a circuit for blocking AC signals amplified by either of the FET stages from passing into DC current supply lines between the FETs and between the power source and one of the FETs.
A bias circuit comprising a first n-channel FET and a second n-channel FET, an NPN bipolar transistor, the emitter of the bipolar transistor being connected to ground, the collector of the bipolar transistor being connected to the source of the first FET, a bypass capacitor connected between the collector and ground, a first resistor having a node connected to the drain of the first FET, a first coupling capacitor coupled between another node of the first resistor and the gate of the second FET, a circuit for applying a bias voltage to the gate of the second FET, a pair of chokes connected in series having one end node connected to the junction of the first coupling capacitor and the first resistor, a second bypass capacitor connected between the junction of the chokes and ground, a sensing resistor connected between another end node of the chokes and the source of the second FET, a third bypass capacitor connected between the source of the second FET and ground, a second resistor connected between the drain of the second FET and a terminal of a further choke, another terminal of the further choke being connected to a positive node of a power supply, a pair of resistors connected in series between the source of the second FET and ground, an input of an operational amplifier connected to a junction of the pair of resistors, another input of the operational amplifier connected to a junction of the sensing resistor and the pair of chokes, the output of the operational amplifier being connected to the base of the bipolar transistor, an input circuit for applying an input signal to the gate of the first FET, and an output circuit AC coupling an output signal connected to the junction of the second load resistor and the further choke.
A bias circuit comprising a first n-channel FET and a second n-channel FET, the source of the first FET being connected to ground, a first resistor having a node connected to the drain of the first FET, a first coupling capacitor coupled between another node of the first resistor and the gate of the second FET, a circuit for applying a bias voltage to the gate of the second FET, a pair of chokes connected in series having one end node connected to the junction of the first coupling capacitor and the first resistor, a second bypass capacitor connected between the junction of the chokes and ground, a sensing resistor connected between another end node of the chokes and the source of the second FET, a third bypass capacitor connected between the source of the second FET and ground, a second resistor connected between the drain of the second FET and a terminal of a further choke, another terminal of the further choke being connected to a positive node of a power supply, a pair of resistors connected in series between the source of the second FET and ground, an input of an operational amplifier connected to a junction of the pair of resistors, another input of the operational amplifier connected to a junction of the sensing resistor and the pair of chokes, the output of the operational amplifier being connected to an input of a charge pump, and output of the charge pump being connected via a bias resistor to the gate of the first FET, an input circuit for AC coupling an input signal to the gate of the first FET, and an output circuit AC coupling an output signal connected to the junction of the second load resistor and the further choke.
A bias circuit comprising a first n-channel FET and a second n-channel FET, an NPN bipolar transistor, the emitter of the bipolar transistor being connected to ground, the collector of the bipolar transistor being connected to the source of the first FET, a bypass capacitor connected between the collector and ground, a first resistor having a node connected to the drain of the first FET, a first coupling capacitor coupled between another node of the first resistor and the gate of the second FET, a circuit for applying a bias voltage to the gate of the second FET, a pair of chokes connected in series having one end node connected to the junction of the first coupling capacitor and the first resistor, a second bypass capacitor connected between the junction of the chokes and ground, a sensing resistor connected between another end node of the chokes and the source of the second FET, a third bypass capacitor connected between the source of the second FET and ground, a second resistor connected between the drain of the second FET and a terminal of a further choke, another terminal of the further choke being connected to a positive node of a power supply, a pair of resistors connected in series between the junction of the pair of chokes and the sensing resistor and ground, an input of an operational amplifier connected to the junction of the pair of resistors, a further pair of resistors connected in series between an opposite end of the sensing resistor and an output of the operational amplifier, another input of the operational amplifier connected to the junction of the further pair of resistors, the output of the operational amplifier being connected to an input of a second operational amplifier, the output of the second operational amplifier being connected to the base of the bipolar transistor, a bandgap reference voltage generator being connected to another input of the second operational amplifier, an input circuit for applying an input signal to the gate of the first FET, and an output circuit AC coupling an output signal connected to the junction of the second load resistor and the further choke.
A bias circuit for a pair of field effect transistor (FET) stages comprising a circuit for AC coupling a signal amplified by a first stage to the input of a second stage, a power source for supplying DC operating current to both of the stages in series, a circuit for sensing operating current drawn by the second stage and in response thereto for controlling bias of the first stage, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit, and a current source or sink for fixing the DC current passing through the stages in series, and a circuit for blocking AC signals amplified by the first stage from being passed via a DC operating current path to the second stage, whereby the same DC operating current is passed through both first and second stages and is blocked from passing through the AC coupling circuit.
Dependencies are inferred from the claim text.