Charge coupled devices

A charge coupled device comprising:

• a transfer electrode portion having a first gate electrode, a second gate electrode and a third gate electrode;
• a charge transfer portion located in a semiconductor substrate under said first, second and third gate electrodes, and having a first potential area formed in said semiconductor substrate under said second gate electrode and a second potential area formed in said semiconductor substrate under said third gate electrode;
• and
• a first clock terminal connected to said first and third gate electrodes, and a second clock terminal connected to said second gate electrode;
• wherein said second gate electrode has a first end overlapping a first end of said first gate electrode and a second end which is disposed between said charge transfer portion and at least part of a gate electrode of an adjacent group of first, second and third gate electrodes;
• wherein said third gate electrode has a first end overlapping a second end of said first gate electrode;
• wherein the length of said second gate electrode that is in contact with the substrate is equal to the sum of the lengths of said first and third gate electrodes that is in contact with the substrate;
• and
• wherein an end portion of said first potential area is aligned with an end portion of said first gate electrode and the other end portion of said first potential area is aligned with a middle portion of said second gate electrode, and the end portions of said second potential area are aligned with the other end portion of said first gate electrode and an end portion of a gate electrode in an adjacent group of first, second and third gate electrodes.

A charge coupled device comprising:

• a transfer electrode portion having a plurality of groups of first, second and third gate electrodes, wherein in each of said groups a first end of said second gate electrode overlaps a first end of said first gate electrode, a first end of said third gate electrode overlaps a second end of said first gate electrode and a second end of said third gate electrode overlaps a second end of the second gate electrode in an adjacent group of first, second and third gate electrodes;
• a charge transfer portion located in a semiconductor substrate under said plurality of groups of first, second and third gate electrodes;
• first and second clock terminals connected to said transfer electrode portion;
• a plurality of first and second potential areas formed in said semiconductor substrate, wherein said first potential areas are formed under said second gate electrodes and wherein said second potential areas are formed under said third gate electrodes;
• and
• wherein in each of said groups an end portion of said first potential area is aligned with an end portion of said first gate electrode and the other end portion of said first potential area is aligned with a middle portion of said second gate electrode, and wherein the end portions of said second potential area are aligned with the other end portion of said first gate electrode and an end portion of the second gate electrode in an adjacent group of first, second and third gate electrodes.

A charge coupled device array comprising:

• a plurality of overlapping charge coupled devices, wherein each of said charge coupled devices comprises:
• a transfer electrode portion having a first gate electrode, a second gate electrode and a third gate electrode,
• a charge transfer portion located in a semiconductor substrate under said first, second and third gate electrodes;
• an insulating layer disposed between said transfer electrode portion and said charge transfer portion;
• and
• a clock portion having a first clock terminal connected to said first and third gate electrodes, and a second clock terminal connected to said second gate electrode;
• and
• wherein said second gate electrode and said third gate electrode partially overlap said first gate electrode, and wherein the length of said second gate electrode that is in contact with the insulating layer is equal to the sum of the lengths of said first and third gate electrodes that is in contact with the insulating layer.