On-chip error detection and correction system for an embedded non-volatile memory array and method of operation

A method for implementing error detection within a memory array, the method comprising the steps of:

• generating a first column parity vector reflecting bit parity information of each column of the memory array and storing the first column parity vector into a parity storage portion of the memory array;
• generating a first row parity vector reflecting bit parity information of each row of the memory array and storing the first row parity vector into the parity storage portion of the memory array, wherein generating the first column parity vector and first row parity vector is performed by a parity circuit;
• and
• accessing the memory array to generate a second row parity vector and a second column parity vector and using the second row parity vector and column parity vector along with the parity storage portion of the memory array to detect data errors within the memory array over time.

A method for implementing error detection within a memory array, the method comprising:

• (a) addressing a selected row in the memory array;
• (b) providing each bit within the selected row of the memory array in parallel as a column bit to a unique one of a plurality of one-bit parity capture circuits to capture an incremental parity state;
• (c) assigning a new selected row as the selected row;
• (d) cycling through steps (b)-(d) until a column parity vector is generated collectively in the one-bit parity capture circuits;
• (e) writing the column parity vector into a first portion of the memory array;
• (f) generating a row parity vector from data within rows of the memory array and writing the row parity vector into a second portion of the memory array;
• and
• (g) accessing the memory array to use the row parity vector and column parity vector along with the first and second portions of the memory array to detect data errors within the memory array over time.

A method for implementing error detection within a memory array, the method comprising:

• (a) addressing a selected row in the memory array;
• (b) providing each bit within the selected row of memory through a set of serially-coupled logic gates where an output of the serially-coupled logic gates is coupled to a first storage element of a shift register;
• (c) latching the output of the serially-coupled logic gates into the first storage element of the shift register;
• (d) shifting data in the shift register at some point in time to preserve the output of the serially-coupled logic gates in the shift register;
• (e) assigning a new selected row as the selected row;
• (f) cycling through steps (b)-(f) until the row parity vector is fully generated in the shift register;
• (g) writing the row parity vector into the first portion of the memory array;
• (f) generating a column parity vector from data within rows of the memory array and writing the column parity vector into a second portion of the memory array:
• and
• (g) accessing the memory array and using the row parity vector and column parity vector alone with the first and second portions of the memory array to detect data errors within the memory array over time.

A method for implementing error detection within a memory array, the method comprising:

• generating column parity information from data within columns of the memory array and writing the column parity information into a first portion of the memory array;
• generating row parity information from data within rows of the memory array and writing the row parity information into a second portion of the memory array;
• and
• accessing the memory array to generate a row parity vector and a column parity vector and using the row parity vector and column parity vector along with the first and second portions of the memory array to detect data errors within the memory array over time, wherein the accessing is performed by using a circuit that can be selectively configured to:
• (1) either generate a plurality of parity bits in parallel to each other using a plurality of parallel-coupled linear feedback registers (LFRs) having at least one flip-flop each or generate and serial shift parity bits in a serial manner;
• and (2) process error vectors to more accurately identify a row and/or column position of an error in the memory array.

A method for implementing error detection on-chip with a memory array, wherein the memory array has M rows and N columns the method comprising the steps of:

• detecting an error row wherein the error row is whichever of the M rows of memory contains an error;
• generating a column error vector having N bits wherein each of the N bits is either a first logic state when that column position in the error row contains no error or a second logic state when that column position in the error row contains the error;
• reading a content of the error row and adding the content of the error row with the column error vector to obtain a corrected content for the error row;
• and
• writing the corrected content back into the error row where the error row becomes a corrected row.

An apparatus comprising:

• a CPU;
• and
• a memory coupled to the CPU, the memory comprising:
• a memory array having a M rows and N columns of memory cells for storage of functional data and one or more additional rows of memory to store parity information;
• decoder circuitry coupled to the memory array for reading and writing data to certain locations within the memory array;
• sense amplifiers coupled to input/output data lines of the memory array;
• a capture circuit coupled to the sense amplifiers;
• a parity controller coupled to the capture circuit and the decoder circuitry;
• and
• wherein the parity controller controls the decoder circuitry and the capture circuit so that parity information is generated for the M rows and the N columns, row parity information reflecting parity of bits in rows of the memory and column parity information reflecting parity of columns of the memory, where the row parity information and column parity information are written into the additional rows of the memory upon an initiation event, and wherein the parity controller controls the decoder circuitry and the capture circuit so that parity vectors are generated for the M rows and the N columns so that, upon a parity-checking trigger event, the parity vectors are compared to the additional rows of memory to determine if the memory contains failures.