Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability

A microprocessor, comprising:

• a memory system for outputting data in response to an address, wherein the memory system is further operable to receive a prefetch request having a predicted target data address;
• a data fetching execution unit operative to compute a target data address and fetch data from said memory system at said target data address in response to a data fetching instruction;
• a load target circuit connected to said memory system for generating said predicted target data address, operative to compare each target data address with a corresponding predicted target data address, and comprising a plurality of entries, wherein each of the plurality of entries comprises:
• an address tag indicating a memory address of a corresponding data fetching instruction;
• a pointer indicating a corresponding predicted target data address;
• and
• a past predicted address accuracy portion storing a value indicating a past predicted accuracy of the corresponding predicted target data address computed from a history of results of said comparisons of said predicted target data address and said corresponding target data address;
• said load target circuit operative to compare a corresponding memory address of a decoded data fetching instruction with each address tag;
• and
• said load target circuit operative to issue a prefetch request to said memory system for data at a corresponding predicted target data address upon a match of said memory address of a decoded data fetching instruction and said address tag of one of said entries.

A microprocessor, comprising:

• a memory system for outputting data in response to an address, wherein the memory system is further operable to receive a prefetch request having a predicted target data address, said memory system including a bus interface unit connected to an external memory and a cache memory;
• a data fetching execution unit operative to compute a target data address and to fetch data from said memory system at said target data address in response to a data fetching instruction;
• a load target circuit operative to detect whether each data fetching instruction generates a cache hit or a cache miss, said load target buffer comprising a plurality of entries, wherein each of the plurality of entries comprises:
• an address tag for indicating a memory address of a corresponding data fetching instruction;
• a pointer for indicating a corresponding predicted target data address;
• and
• a past prefetch usefulness value indicating whether at least one prior past incident of the data fetching instruction corresponding to the entry generated a cache hit or a cache miss;
• said load target circuit operative to compare a corresponding memory address of a decoded data fetching instruction with each address tag;
• and
• said load target circuit operative to issue a prefetch request to said memory system for data at a corresponding predicted target data address upon a match of said memory address of a decoded data fetching instruction and said address tag of one of said entries.

A method of operating a microprocessor having an instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, target data address prediction information and an indication of past prediction accuracy;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer:
• generating a prefetch request to a memory system at an address calculated from the target address prediction information;
• updating the indication of past prediction accuracy to indicate more accurate past prediction;
• and
• if the memory address of a data fetching instruction does not match the address tags of any entry in the load target buffer:
• identifying a group of entries in the load target buffer on the microprocessor, wherein the identified group is a group in which target data address prediction information corresponding to the received data fetching instruction may be stored based on the corresponding memory address;
• identifying a least recently used entry from the identified group of entries;
• in response to the value for indicating a past predicted accuracy falling below a predetermined threshold, overwriting the identified entry with target data address prediction information corresponding to the received data fetching instruction;
• updating the indication of past prediction accuracy to indicate less accurate past prediction;
• and
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline computing a target data address;
• and
• fetching data from said memory system at said target data address in response to a data fetching instruction.

A method of operating a microprocessor having, a cache memory, an instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, target data address prediction information and an indication of past prediction usefulness;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer:
• generating a prefetch request to a memory system at an address calculated from the target address prediction information;
• and
• if the memory address of a data fetching instruction does not match the address tag of any entry in the load target buffer:
• identifying a group of entries in the load target buffer on the microprocessor, wherein the identified group is a group in which target data address prediction information corresponding to the received data fetching instruction may be stored based on the corresponding memory address;
• identifying a least recently used entry from the identified group of entries;
• in response to the indication of past prefetch usefulness falling below a predetermined threshold, overwriting the identified entry with target data address prediction information corresponding to the received data fetching instruction;
• and
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline:
• computing a target data address;
• fetching data from said memory system at said target data address in response to a data fetching instruction;
• detecting whether each data fetching instruction generates a cache hit or a cache miss;
• and
• updating the indication of past prefetch usefulness to indicate more usefulness upon a cache hit and to indicate less usefulness upon a cache miss.

A method of operating a microprocessor having, a cache memory, an instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, target data address prediction information, an indication of past prediction accuracy and an indication of past prediction usefulness;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer:
• generating a prefetch request to a memory system at an address calculated from the target address prediction information;
• updating the indication of past prediction accuracy to indicate more accurate past prediction;
• and
• if the memory address of a data fetching instruction does not match the address tags of any entry in the load target buffer:
• identifying a group of entries in the load target buffer on the microprocessor, wherein the identified group is a group in which target data address prediction information corresponding to the received data fetching instruction may be stored based on the corresponding memory address;
• identifying a least recently used entry from the identified group of entries;
• updating the indication of past prediction accuracy to indicate less accurate past prediction;
• in response to a combination of the value for indicating a past predicted accuracy combined with the past prefetch usefulness value falling below a predetermined threshold, overwriting the identified entry with target data address prediction information corresponding to the received data fetching instruction;
• and
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline:
• computing a target data address;
• fetching data from said memory system at said target data address in response to a data fetching instruction;
• detecting whether each data fetching instruction generates a cache hit or a cache miss;
• and
• updating the indication of past prefetch usefulness to indicate more usefulness upon a cache hit and to indicate less usefulness upon a cache miss.

A method of operating a microprocessor having an instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, target data address prediction information and an indication of past prediction accuracy;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer:
• generating a prefetch request to a memory system at an address calculated from the target address prediction information;
• updating the indication of past prediction accuracy to indicate more accurate past prediction;
• and
• if the memory address of a data fetching instruction does not match the address tags of any entry in the load target buffer:
• identifying a group of entries in the load target buffer on the microprocessor, wherein the identified group is a group in which target data address prediction information corresponding to the received data fetching instruction may be stored based on the corresponding memory address;
• identifying a particular entry from the identified group of entries;
• in response to the value for indicating a past predicted accuracy falling below a predetermined threshold, overwriting the identified entry with target data address prediction information corresponding to the received data fetching instruction;
• updating the indication of past prediction accuracy to indicate less accurate past prediction;
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline;
• computing a target data address;
• and
• fetching data from said memory system at said target data address in response to a data fetching instruction.

A method of operating a microprocessor having, a cache memory, a n instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, target data address prediction information and an indication of past prediction usefulness;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer:
• generating a prefetch request to a memory system at an address calculated from the target address prediction information and
• if the memory address of a data fetching instruction does not match the address tag of any entry in the load target buffer:
• identifying a group of entries in the load target buffer on the microprocessor, wherein the identified group is a group in which target data address prediction information corresponding to the received data fetching instruction may be stored based on the corresponding memory address;
• identifying a least recently used entry from the identified group of entries;
• in response to the indication of past prefetch usefulness falling below a predetermined threshold, overwriting the identified entry with target data address prediction information corresponding to the received data fetching instruction;
• and
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline:
• computing a target data address;
• fetching data from said memory system at said target data address in response to a data fetching instruction;
• detecting whether each data fetching instruction generates a cache hit or a cache miss;
• and
• updating the indication of past prefetch usefulness to indicate more usefulness upon a cache hit and to indicate less usefulness upon a cache miss.

A method of operating a microprocessor having, a cache memory, an instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, target data address prediction information, an indication of past prediction accuracy and an indication of past prediction usefulness;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer:
• generating a prefetch request to a memory system at an address calculated from the target address prediction information;
• updating the indication of past prediction accuracy to indicate more accurate past prediction;
• and
• if the memory address of a data fetching instruction does not match the address tags of any entry in the load target buffer:
• identifying a group of entries in the load target buffer on the microprocessor, wherein the identified group is a group in which target data address prediction information corresponding to the received data fetching instruction may be stored based on the corresponding memory address;
• identifying a particular entry from the identified group of entries;
• updating the indication of past prediction accuracy to indicate less accurate past prediction;
• in response to a combination of the value for indicating a past predicted accuracy combined with the past prefetch usefulness value falling below a predetermined threshold, overwriting the identified entry with target data address prediction information corresponding to the received data fetching instruction;
• and
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline:
• computing a target data address;
• fetching data from said memory system at said target data address in response to a data fetching instruction;
• detecting whether each data fetching instruction generates a cache hit or a cache miss;
• and
• updating the indication of past prefetch usefulness to indicate more usefulness upon a cache hit and to indicate less usefulness upon a cache miss.

A method of operating a microprocessor having an instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, a plurality of address pointers each storing a corresponding target data address and an indication of a next address pointer;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer:
• generating a prefetch request to a memory system at an address corresponding to the target data address stored in the address pointer indicated by the indication of a next address pointer;
• and
• updating the indication of a next address pointer to indicate a next address pointer in a circular sequence of the plurality of address pointers;
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline;
• computing a target data address;
• and
• fetching data from said memory system at said target data address.

A method of operating a microprocessor having an instruction pipeline and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag, a plurality of address pointers each storing a corresponding target data address, an indication of a next address pointer, a mode indicator indicating a looping mode or a striding/looping mode, a stride length, a stride threshold and a stride counter;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer and the mode indicator indicates a looping mode:
• generating a prefetch request to a memory system at an address corresponding to the target data address stored in the address pointer indicated by the indication of a next address pointer;
• and
• updating the indication of a next address pointer to indicate a next address pointer in a circular sequence of the plurality of address pointers;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer and the mode indicator indicates a striding/looping mode and the stride counter is zero:
• initializing the stride counter with the stride threshold;
• generating a prefetch request to the memory system at an address corresponding to the target data address stored in the address pointer indicated by the indication of a next address pointer;
• adding the stride length to the address pointer indicated by the indication of a next address pointer;
• decrementing the stride counter;
• and
• if the stride counter has decremented to zero restoring the address pointer to an initial value and updating the indication of a next address pointer to indicate a next address pointer in a circular sequence of the plurality of address pointers;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer and the mode indicator indicates a striding/looping mode and the stride counter is not zero:
• generating a prefetch request to the memory system at an address corresponding to the target data address stored in the address pointer indicated by the indication of a next address pointer;
• adding the stride length to the address pointer indicated by the indication of a next address pointer;
• decrementing the stride counter;
• and
• if the stride counter has decremented to zero restoring the address pointer to an initial value and updating the indication of a next address pointer to indicate a next address pointer in a circular sequence of the plurality of address pointers;
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline;
• computing a target data address;
• and
• fetching data from said memory system at said target data address.

A method of operating a microprocessor having an instruction pipeline, a cache memory and a load target buffer, comprising the steps of:

• storing a plurality of entries in the load target buffer, each entry including an address tag and target data address prediction information;
• receiving a data fetching instruction in the instruction pipeline, wherein the data fetching instruction has a corresponding memory address;
• upon a data fetching instruction reaching a first predetermined stage in the instruction pipeline comparing a memory address of the data fetching instructions with an address tag of each entry in the load target buffer;
• if the memory address of a data fetching instruction matches the address tag of an entry in the load target buffer
• generating a prefetch request to the cache memory at an address corresponding to the target data address stored in the address pointer indicated by the indication of a next address pointer;
• determining if data at the target data address is stored in the cache memory;
• and
• if the data at the target data address is not stored in the cache memory initiating a cache line fill operation from a higher level memory;
• upon a data fetching instruction reaching a second predetermined state in the instruction pipeline;
• computing a target data address;
• and
• fetching data from said memory system at said target data address.