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US 6,215,726 B1Granted
Semiconductor device with internal clock generating circuit capable of generating internal clock signal with suppressed edge-to-edge jitter
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakashi Kubo
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Abstract
A data/strobe output buffer performs data output according to an outputting internal dock signal DLLCLK from a DLL (Delayed Locked Loop) circuit and an output enable signal. During a time period for a data reading operation including a time period in which the output enable signal is in an active state, a control circuit suspends a phase adjusting operation of the clock signal DLLCLK in the DLL circuit. Thus, occurrence of edge-to-edge jitter in the internal clock signal defining the timing of data output can be suppressed.
Claims17
A semiconductor device, comprising:
- an internal clock generating circuit receiving a first clock signal corresponding to an external clock signal, for generating a second clock signal in synchronization with said first clock signal, said internal clock generating circuit including phase adjusting means for detecting a phase difference between the first and second clock signals to adjust the phase of said second clock signal based on a detection result;
- an output circuit activated in a data output mode, for externally outputting data in synchronization with said second clock signal;
- and
- a clock control circuit for suspending a phase adjusting operation of said phase adjusting means in said data output mode, at least during a time period in which said output circuit is activated.
1 more element
A semiconductor device, comprising:
- a clock generating circuit for generating a first clock signal in synchronization with a second clock signal corresponding to an externally supplied clock signal, said clock generating circuit including phase adjusting means for detecting a phase difference between the first and said second clock signals to adjust a phase of said first clock signal according to a detection result;
- an internal circuit operating in synchronization with said first clock signal;
- and
- a clock control circuit for activating a phase adjusting operation of said phase adjusting means in response to an activation control signal.
1 more element
Dependencies are inferred from the claim text.