Multi-level memory cell device and method for self-converged programming

A non-volatile, multiple level, self-converging programmable memory cell device comprising:

• a floating gate memory cell having a node coupled to a memory cell current source with a memory cell current source voltage;
• a reference cell having a node coupled to a reference cell current source with a reference cell current source voltage;
• wherein the memory and reference cells each have a source node, a drain node, and a gate node, the memory and reference cell gate nodes are connected via a common wordline, the memory and reference cell drain nodes receive common inputs, and the memory and reference cell source nodes are coupled to the respective memory and reference cell current sources;
• further including a comparator coupled to receive input signals from the memory cell current source voltage and the reference cell current source voltage, the comparator producing a signal representing the difference between the input signals;
• and
• a program controller for applying pro ramming signals to the memory and reference cell, the program controller responsive to the signal from the comparator.

A non-volatile, multiple level, self-converging programmable memory cell device comprising:

• a floating gate memory cell having a node coupled to a memory cell current source with a memory cell current source voltage;
• a reference cell having a node coupled to a reference cell current source with a reference cell current source voltage wherein the reference cell includes a floating gate memory cell with the control gate and floating gate coupled together;
• a comparator coupled to receive input signals from the memory cell current source voltage and the reference cell current source voltage, the comparator producing a signal representing the difference between the input signals;
• and
• a program controller for applying programming signals to the memory and reference cell, the program controller responsive to the signal from the comparator.

A non-volatile, multiple level, self-converging programmable memory cell device comprising:

• a floating gate memory cell, selectable from an array of memory cells, the memory cell having a drain, source and gate node;
• a reference cell, selectable from an array of reference cells, the reference cell having a drain, source, and gate nodes, wherein the memory and reference cell gate nodes are coupled via a common wordline, and the memory and reference cell drain nodes are switchably coupled to a voltage input;
• a comparator which receives input signals from the memory and reference cell source nodes and outputs a difference between the input signals;
• and
• a program controller for applying programming inputs to the coupled memory and reference cells, the controller responsive to the output of the comparator.

A method for multiple level, self-converged programming of a memory cell device including a floating gate memory cell having a threshold voltage and source node with a current source voltage, a non-programmable reference cell having a threshold voltage and source node with a current source voltage, a comparator with at least two inputs and one output, the method comprising the steps of:

• setting a threshold voltage for the reference cell;
• undergoing programming steps to program the memory cell to a desired level corresponding to the threshold voltage;
• comparing the memory cell current source voltage and the reference cell current source voltage by inputting the signals into the comparator, wherein the memory cell source voltage will converge to the level of the reference cell source voltage;
• using the output of the comparator to provide program control signals which cease programming operations.

A non-volatile, multiple level, self-converging programmable memory cell device comprising:

• a floating gate memory cell having a node coupled to a memory cell current source with a memory cell current source voltage;
• a reference cell having a node coupled to a reference cell current source with a reference cell current source voltage;
• a comparator coupled to receive input signals from the memory cell current source voltage and the reference cell current source voltage, the comparator producing a signal representing the difference between the input signals;
• and
• a program controller for applying programming signals to the memory and reference cell, the program controller responsive to the signal from the comparator wherein the memory cell has a threshold voltage and the reference cell has a threshold voltage, and the memory cell threshold voltage will converge to the threshold voltage of the reference cell.