Process of making densely patterned silicon-on-insulator (SOI) region on a wafer

A process for making dense patterned silicon-on-insulator for merged logic and DRAM circuitry on a wafer, the process comprising the steps of:

• (a) providing a silicon-on-insulator structure, the silicon-on-insulator structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer;
• (b) forming a nitride layer on top of the silicon-on-insulator structure;
• (c) selectively etching portions of the nitride layer to expose the silicon-on-insulator structure, a portion of the nitride layer not etched forming a silicon-on-insulator region;
• (d) selectively etching a portion of the exposed silicon-on-insulator structure to expose the silicon substrate;
• (e) growing an epitaxial layer on top of the exposed silicon substrate to form a bulk region;
• (f) removing the nitride portion above the silicon-on-insulator structure;
• and
• (g) forming the logic circuitry above the silicon-on-insulator region and the DRAM circuitry above the bulk region.

A process for making a silicon-on-insulator region and a bulk region in a semiconductor device, the process comprising the steps of:

• (a) providing a silicon-on-insulator structure, the silicon-on-insulator structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer;
• (b) forming a nitride layer on top of the silicon-on-insulator structure;
• (c) selectively etching portions of the nitride layer to expose the silicon-on-insulator structure, a portion of the nitride layer not etched forming the silicon-on-insulator region and forming a shallow trench isolation to bound the silicon-on-insulator region;
• (d) selectively etching a portion of the exposed silicon-on-insulator structure to expose the silicon substrate;
• (e) growing an epitaxial layer on top of the exposed silicon substrate to form the bulk region;
• and
• (f) removing the nitride portion above the silicon-on-insulator structure.

A process for making a silicon-on-insulator region and a bulk region in a semiconductor device, the process comprising the steps of:

• (a) providing a silicon-on-insulator structure, the silicon-on-insulator structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer;
• (b) forming a nitride layer on top of the silicon-on-insulator structure;
• (c) selectively etching portions of the nitride layer to expose the silicon-on-insulator structure, a portion of the nitride layer not etched forming the silicon-on-insulator region;
• (d) selectively etching a portion of the exposed silicon-on-insulator structure to expose the silicon substrate;
• (e) growing an epitaxial layer on top of the exposed silicon substrate to form the bulk region;
• (f) removing the nitride portion above the silicon-on-insulator structure;
• and
• (g) forming a first type of circuit above the silicon-on-insulator region and a second type of circuit above the bulk region, wherein the first type of circuit is a logic circuit and the second type of circuit is a DRAM circuit.