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US 6,212,671 B1Granted
Mask pattern data producing apparatus, mask pattern data producing method and semiconductor integrated circuit device
AssigneesMitsubishi Electric System LSI Design Corporation, Mitsubishi Denki Kabushiki Kaisha
InventorsYusuke Kanehira, Takao Satoh, Nobuhide Naritomi
Life of this patent
Estimating the term…
Abstract
A well wall of a second type of conduction is formed so as to surround a first IC formed in a first IC forming region specified by a region specifying means and to extend from a surface of a semiconductor substrate to a bottom well on the basis of information about the first IC forming region and information about the bottom well in a mask pattern produced by a bottom well mask pattern producing means.
Claims13
A mask pattern data producing apparatus comprising:
- means for specifying a first IC forming region and a second IC forming region on a surface of a semiconductor substrate of a first conduction type;
- MOS transistors of a second conduction type formed in first well regions of the first IC forming region for charging at a first substrate potential, said first well regions being of a first conduction type;
- MOS transistors of the second conduction type formed in second well regions of the second IC forming region for charging at a second substrate potential that is different from the first substrate potential, said second well regions being of the first conduction type;
- means for producing a first mask pattern for forming a bottom well of the second type of conduction under the first well regions in the entire first IC forming region of the semiconductor substrate;
- and
- means for producing a second mask pattern for forming a well wall of the second type of conduction surrounding a first IC formed in the first IC forming region and extending from the surface of the semiconductor substrate to the bottom well on the basis of information about the first IC forming region specified by the means for specifying and information about the bottom well corresponding to the mask pattern producing by the means for producing a first mask pattern.
3 more elements
A mask pattern data producing apparatus comprising:
- means for specifying a first IC forming region having a first IC formed therein and a second IC forming region having a second IC is formed therein;
- a semiconductor substrate of a first conduction type having the first IC forming region and the second IC forming region on a surface thereof;
- said first IC comprising a plurality of cells having a predetermined logic value, wherein at least some of the cells are formed of MOS transistors of a second conductor type formed in first well regions of the first conduction type for charging at a first substrate potential, and wherein at least part of the second IC is formed of MOS transistors of the second conduction type formed in second well regions of the first conduction type for charging at a second substrate potential that is different from the first substrate potential;
- means for specifying a layout for the plurality of cells in the first IC forming region based on logical information describing the operations of the first IC;
- means for specifying wiring routes in the first IC forming region based on logical information describing the operations of the first IC and cell information about the plurality of cells;
- means for producing a first mask pattern for forming a bottom well of the second conduction type under the first well regions in the entire first IC forming region of the semiconductor substrate;
- and
- means for producing a second mask pattern for forming a well wall of the second conduction type surrounding the first IC and extending from the surface of the semiconductor substrate to the bottom well based on information about the first IC forming region specified by said means for specifying a first IC forming region and information about the bottom well corresponding to the mask pattern produced.
5 more elements
A semiconductor IC device comprising:
- a semiconductor substrate of a first type of conduction having on a surface thereof a first IC forming region in which a first IC is formed and a second IC forming region in which a second IC is formed;
- first well regions of the first type of conduction formed in the first IC forming region;
- MOS transistors of a second type of conduction formed as components of the first IC in the first well regions;
- second well regions of the first type of conduction formed in the second IC forming region;
- MOS transistors of the second type of conduction formed as components of the second IC in the second well regions;
- a well potential isolation region having a bottom well of the second type of conduction underlying the first well regions in the entire first IC forming region of the semiconductor substrate, and a well wall surrounding the first IC and extending from the surface of the semiconductor substrate to the bottom well;
- a first wiring layer formed on the surface of the semiconductor substrate and electrically connected to surfaces of the first well regions to charge the first well regions at a ground potential;
- a second wiring layer formed on the surface of the semiconductor substrate and electrically connected to surfaces of the second well regions to charge the second well regions at a negative potential;
- and
- a third wiring layer formed on the surface of the semiconductor substrate and electrically connected to a surface of the well potential isolation region to charge the well potential isolation region at a positive potential.
7 more elements
Dependencies are inferred from the claim text.