Back to results
US 6,212,667 B1Granted
Integrated circuit test coverage evaluation and adjustment mechanism and method
AssigneeInternational Business Machines Corporation
InventorsCharles Porter Geer, Ronald Nick Kalla, Jerome Martin Meyer, Shmuel Ur
Life of this patent
Estimating the term…
Abstract
Testcases are run to test the design of an integrated circuit. The coverage of the testcases is evaluated and compared against one or more microarchitecture models that define the behavior of a portion of the integrated circuit. If the coverage of the testcases is not adequate, new testcases are generated to test the previously untested behavior specified in the microarchitecture models.
Claims26
An apparatus comprising:
- at least one processor;
- a memory coupled to the at least one processor;
- an integrated circuit design residing in the memory;
- a plurality of testcases residing in the memory for testing the integrated circuit design;
- and
- a test coverage evaluation and adjustment mechanism residing in the memory and executed by the at least one processor, the test coverage evaluation and adjustment mechanism evaluating test coverage for the plurality of testcases, the test coverage comprising a measure of how completely the plurality of testcases tests the integrated circuit design, the test coverage evaluation and adjustment mechanism causing new testcases to be automatically generated that are biased to more thoroughly test the integrated circuit design if the test coverage is inadequate.
3 more elements
An apparatus comprising:
- at least one processor;
- a memory coupled to the at least one processor;
- an integrated circuit design residing in the memory;
- a plurality of testcases residing in the memory for testing the integrated circuit design;
- and
- means for automatically generating at least one new testcase to test the integrated circuit design based on comparing 1) the results of applying the plurality of testcases to the integrated circuit design with 2) at least one microarchitecture model of the integrated circuit design.
3 more elements
A method for testing an integrated circuit design, the method comprising the step of:
- automatically generating at least one new testcase to test the integrated circuit design based on comparing 1) the results of applying a plurality of testcases to the integrated circuit design with 2) at least one microarchitecture model of the integrated circuit design.
A method for testing an integrated circuit design, the method comprising the steps of:
- (A) applying a plurality of testcases to a simulation model of the integrated circuit design;
- (B) providing at least one microarchitecture model of the integrated circuit design, the microarchitecture model defining behavior for at least a portion of the integrated circuit design;
- (C) comparing the results of applying the plurality of testcases to the simulation model of the integrated circuit design to the at least one microarchitecture model;
- and
- (D) automatically generating at least one new testcase that provides improved test coverage based on the compared results.
2 more elements
A computer readable program product comprising:
- (A) a test coverage evaluation and adjustment mechanism that evaluates test coverage for a plurality of testcases for an integrated circuit design, the test coverage comprising a measure of how completely the plurality of testcases tests the integrated circuit design, the test coverage evaluation and adjustment mechanism causing new testcases to be automatically generated that are biased to more thoroughly test the integrated circuit design if the test coverage is inadequate;
- and
- (B) computer readable signal bearing media bearing the test coverage evaluation and adjustment mechanism.
An apparatus comprising:
- at least one processor:
- a memory coupled to the at least one processor;
- an integrated circuit design residing in the memory:
- a testcase generator that automatically generates a first plurality of testcases for testing the integrated circuit design according to information in a testcase definition file;
- a gate level cycle simulator residing in the memory that applies the first plurality of testcases to the integrated circuit design residing in the memory;
- a test coverage evaluation and adjustment mechanism residing in the memory and executed by the at least one processor, the test coverage evaluation and adjustment mechanism evaluating test coverage for the first plurality of testcases as applied by the gate level cycle simulator, the test coverage comprising a measure of how completely the first plurality of testcases tests the integrated circuit design, the test coverage evaluation and adjustment mechanism modifying the testcase definition file if the test coverage is inadequate to cause the testcase generator to automatically generate a second plurality of testcases that are biased to more thoroughly test the integrated circuit design, thereby causing the gate level cycle simulator to iteratively apply testcases to the integrated circuit design.
3 more elements
A method for testing an integrated circuit design residing in a memory, the method comprising the step of:
- (1) generating a first plurality of testcases for testing the integrated circuit design according to information in a testcase definition file;
- (2) applying the first plurality of testcases to the integrated circuit design;
- (3) evaluating test coverage of the testcases as applied to the integrated circuit design;
- (4) if the test coverage is inadequate, performing the steps of:
- (4A) modifying the testcase definition file;
- (4B) automatically generating a new plurality of testcases;
- and
- (4C) repeating steps (3) and (4) until the test coverage is adequate.
5 more elements
Dependencies are inferred from the claim text.