Graphic representation of circuit analysis for circuit design and timing performance evaluation

An apparatus for graphic representation of circuit design and timing analysis in a data processing system, comprising:

• a first portion configured to provide a circuit representation stored in a memory of the data processing system, the circuit representation representing a circuit having at least one path with an associated delay;
• a second portion coupled to the first portion and configured to generate a Directed Acyclic Graph (DAG) in the memory in accordance with the circuit representation;
• and
• a third portion coupled to the second portion and configured to display the graphic representation including in the form of a delay chart in accordance with the DAG, the delay chart representing the delay of the circuit Path graphically with an edge comprising a graphically distinct portion whose length is proportional to the delay, the delay chart including one or both of a right-to-left delay chart and a left-to-right delay chart, wherein the delay chart facilitates the design and timing analysis of the circuit.

An apparatus for graphic representation of circuit design and timing analysis in a data processing system, comprising:

• means for providing a circuit representation stored in a memory of the data processing system, the circuit representation representing a circuit having at least one path with an associated delay;
• means coupled to the providing means for generating a [Direct] Directed Acyclic Graph (DAG) in the memory in accordance with the circuit representation;
• and
• means coupled to the generating means for displaying the graphic representation including in the form of a delay chart in accordance with the DAG, the delay chart representing the delay of the circuit path graphically with an edge comprising a graphically distinct portion whose length is proportional to the delay, the delay chart including one or both of a right-to-left delay chart and a left-to-right delay chart, wherein the delay chart facilitates the design and timing analysis of the circuit.

A computer readable medium including instructions for graphic representation of circuit design and timing analysis in a data processing system, the instructions for:

• providing a circuit representation stored in a memory of the data processing system, the circuit representation representing a circuit having at least one path with an associated delay;
• generating a Directed Acyclic Graph (DAG) in the memory in accordance with the circuit representation;
• and
• displaying the graphic representation including in the form of a delay chart in accordance with the DAG, the delay chart representing the delay of the circuit path graphically with an edge comprising a graphically distinct portion whose length is proportional to the delay, the delay chart including one or both of a right-to-left delay chart and a left-to-right delay chart, wherein the delay chart facilitates the design and timing analysis of the circuit.