Efficient power analysis method for logic cells with many output switchings

A power evaluation tool for calculating the dynamic power dissipation of an electronic circuit design under simulation, comprising:

• a receiver responsive to a simulated logic transition signal received from a simulator;
• a first queue responsive to each simulated logic transition and direction that occurs at an input pin corresponding to a cell, said first queue having a two item capacity said first queue capable of storing items in first-in-first-out (FIFO) order;
• a second FIFO queue responsive to each simulated logic transition and direction that occurs at a boundary pin corresponding to said cell, said second queue having a two item capacity, said second queue capable of storing items in FIFO order;
• means for searching a power model for a simple arc that corresponds to said simulated logic transition, said power model corresponding to a cell instance which corresponds to the cell in which said simulated logic transition occurred;
• and
• means for generating an energy value using said simple arc.

A computer system, comprising:

• a simulator for simulating an electronic circuit design;
• a cell library containing power models corresponding to each cell instance used said electronic circuit design;
• a power evaluation tool for calculating the dynamic power dissipation of said electronic circuit design, said power evaluation tool having:
• an application program for execution by one or more processors provided by a computer under direction of an installed operating system program;
• a first queue and second queue pair for each cell instance used in said electronic circuit design;
• said first queue for storing in a FIFO manner each transition and transition direction that occur at an input pin corresponding to said cell instance, said first queue responsive to said application program, and said second queue for storing in a FIFO manner each transition and transition direction that occur at every boundary pin corresponding to said cell instance, said second queue responsive to said application program;
• a receiver responsive to each simulated logic transition signal resulting from the simulation of the electronic circuit;
• means for searching one of said power models in said cell library for a simple arc that corresponds to said simulated logic transition, said one of said power models corresponding to a cell instance which corresponds to the cell in which said simulated logic transition occurred;
• and
• means for generating an energy value using said simple arc.

A program storage device readable by a machine, embodying a program of instructions executable by the machine to perform a method to evaluate power dissipation of an electronic circuit design having at least one cell, the method comprising:

• receiving input information descriptive of the electronic circuit design, said input information including a power model for each cell instance used in the electronic circuit design;
• simulating the electronic circuit design so as to generate a simulated logic transition within the at least one cell;
• storing said simulated logic transition in a first-in-first-out (FIFO) manner in a first queue and a second queue, if said simulated logic transition occurs at an input pin of one of the cells used in the electronic circuit design;
• storing said simulated logic transition in a FIFO manner in said second queue, if said simulated logic transition occurs at an output pin of one of the cells used in the electronic circuit design;
• searching a power model for a simple arc that corresponds to said simulated logic transition, said power model corresponding to a cell instance which corresponds to the cell in which said simulated logic transition occurred in said simulating;
• and
• generating an energy value using said simple arc.