Automated scan chain sizing using Synopsys
AssigneeAdaptec, Inc.
InventorsBrian Thomas Fosco, Bruce Pember
Life of this patent
Estimating the term…
Abstract
A method of configuring scan mode circuitry of an integrated circuit (IC) device includes parsing through an initial file of the scan-flops that are to be included in the scan mode circuitry. The initial file can be prepared with a synthesis tool such as Synopsys. A particular subset of scan-flops are parsed, according to an identified number to be included in each scan chain. A holding tank is created to hold each subset of scan-flops for each scan chain. Each holding tank is then used to form a scan path and to stitch the corresponding scan chain. The parsing of the scan-flops into holding tanks can be performed with a c-shell script. Also, the c-shell script can be called by a Synopsys dc_shell script.
Claims27
A method for designing scan mode circuitry for testing electrical interconnections within an integrated circuit design, the method comprising:
- identifying each one of a plurality of scan-flops that will be part of the scan mode circuitry;
- declaring each one of the plurality of scan-flops as being part of a valid scan path and writing the plurality of scan-flops to an executable file;
- executing a Unix c-shell script for creating a plurality of scan sub-chains from the plurality of scan-flops, such that the creating includes defining a plurality of holding tanks for storing each of the scan sub-chains;
- declaring a scan path for each of the scan sub-chains that are stored in each of the plurality of holding tanks;
- declaring a set of test signals for each of the scan sub-chains;
- and
- stitching each of the scan sub-chains of the plurality of scan-flops that are part of the executable file.
A method for configuring test circuitry on an integrated circuit (IC) device that includes a plurality of scan-flops, to facilitate scan mode testing of the IC device with efficiently maximized fault coverage, comprising:
- identifying a first particular number of scan-flops that is desired to be in a first scan chain;
- parsing through the plurality of scan-flops for the first particular number of scan-flops, using a computer-implemented script, thereby parsing through a first subset of the plurality of scan-flops to be included in the first scan chain;
- and
- listing the first subset of the plurality of scan-flops in a first holding tank to be used to form the first scan chain.
A method for configuring scan mode circuitry of an integrated circuit device, the method comprising:
- preparing an initial file listing a plurality of scan-flops that will be used in the scan mode circuitry;
- creating a holding tank for each of a plurality of scan chains, each holding tank listing a subset of the plurality of scan-flops forming a particular scan chain;
- determining a scan path for each scan chain;
- determining a test vector for each scan chain;
- determining scan signals for each scan chain, including a scan-in signal and a scan-enable signal;
- assigning each scan signal to a port of the integrated circuit device, for facilitating introduction of a scan signal to a scan-flop of each scan;
- and
- stitching each scan chain.
A computer readable medium containing program instructions for configuring test circuitry of an integrated circuit (IC) device to facilitate scan mode testing of the IC device, the computer readable media comprising:
- program instructions for parsing through an initial file that lists a plurality of scan-flops that are to be included in the test circuitry, for a first particular number of scan-flops, thereby defining a first subset of the plurality of scan-flops;
- and
- program instructions for listing the first subset of the plurality of scan-flops to a first subset file that can be used to form a first scan chain.
Dependencies are inferred from the claim text.