Microprocessor including flash memory with its verification simplified
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYuichiro Miwa, Katsunobu Hongo
Life of this patent
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Abstract
A microcomputer including a flash memory and a CPU for carrying out verification of data written into the flash memory. A flash controller suspends the supply of a clock signal to the CPU when it receives a verification command from the CPU, establishes a verification condition, and reads data from the flash memory. After reading the data from the flash memory, it restarts the supply of the clock signal to the CPU so that the CPU receives the data. This makes it unnecessary for a program of the CPU for writing data into the flash memory to be transferred from the flash memory to a RAM, enabling the structure of the program to be simplified.
Claims23
A microcomputer comprising:
- a flash memory;
- a clock generator for generating a clock signal;
- a central processing unit (CPU) for transmitting a verification command when carrying out verification of data in said flash memory while executing a program in response to the clock signal generated by said clock generator;
- condition establishing means for establishing, when it receives the verification command from said CPU, a verification condition and suspending supply of the clock signal to said CPU;
- data read means for reading data from said flash memory when said condition establishing means establishes the verification condition;
- comparing means for comparing the data read from said flash memory with an expected value;
- and
- condition releasing means for releasing said verification condition to restart the supply of the clock sign to said CPU.
A microcomputer comprising:
- a flash memory;
- a clock generator for generating a clock signal;
- a central processing unit (CPU) for transmitting a verification command when carrying out, while executing a program in response to the clock signal generated by said clock generator, verification of data in said flash memory generated by auto-erasure;
- condition establishing means for establishing, when it receives the verification command from said CPU, a verification condition and for suspending supply of the clock signal to said CPU;
- data read means for reading data from said flash memory when said condition establishing means establishes the verification condition;
- decision means for making a decision whether the data read from said flash memory all agree with each other;
- and
- condition releasing means for releasing said verification condition to restart the supply of the clock sign to said CPU.
A method of data verification comprising the steps of:
- transmitting a verification command from a central processing unit (CPU) to a flash controller;
- establishing a verification condition, upon receipt of the verification command, and suspending the supply of a clock signal to the CPU;
- reading data from a flash memory under the verification condition;
- comparing data read from flash memory with an expected value;
- and
- releasing the verification condition, including restarting the supply of the clock signal to the CPU.
Dependencies are inferred from the claim text.