Programmable and flexible power management unit

A computer system comprising:

• a central processing unit (CPU);
• system memory coupled to the CPU;
• a graphics/display controller coupled to the CPU and the system memory, the graphics controller comprising:
• a CPU interface unit (CIF) coupled to the CPU;
• a graphics engine (GE) coupled to the CIF;
• a memory interface unit (MIU) coupled to the GE
• a frame buffer coupled to the MIU;
• a display controller coupled to the MIU;
• a flat panel interface coupled to the display controller;
• a CRT Digital-to-Analog converter (DAC) coupled to the display controller;
• a plurality of phase lock loop circuits;
• and
• a programmable Power Management Unit (PMU) comprising:
• a state machine receiving as inputs state control signals, in response to the state control signals, the state machine selecting one of a number of main power states for the PMU wherein the selected main power state has N sub-states, in response to control signals, the state machine sequencing through the N sub-states of the selected main power state for the PMU, the state machine generating signals indicating the selected main power state and the N sub-states that the state machine is currently in, wherein each sub-state controlling a corresponding module such that the N sub-states are combined to control the corresponding modules according to a desired sequence, wherein the state machine sequencing the N sub-states according to the sequence that is determined by programmable registers;
• and
• a plurality of enable circuits coupled to the corresponding modules, the plurality of enable circuits receiving as inputs the signals from the state machine, the plurality of enable circuits generating signals to control the corresponding modules.

A method to manage power in a circuit comprising:

• in response to state control signals, selecting one of a number of main power states, wherein the selected main power state has N sub-states, each sub-state controlling a corresponding module such that the N sub-states are combined to control the corresponding modules according to a desired sequence;
• in response to control signals, sequencing through the N sub-states of the selected main power state, wherein the N sub-states are sequenced according to a sequence that is determined by programmable registers;
• monitoring current status of the main power state and sub-state;
• generating signals indicating the current status of the selected main power state and sub-state;
• and
• in response to the signals indicating the status of the selected main power state and the sub-state, generating signals to enable selected sub-circuits in the circuit.