US 6,212,628 B1Granted

Mesh connected computer

AssigneeTeraNex, Inc.

InventorsAndrew P. Abercrombie, David A. Duncan, Woodrow Meeker, Michele D. Van Dyke-Lewis

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Abstract

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array. In another aspect, a programmer references images via pointers to image descriptors that include the actual addresses of various bits of multi-bit data. Other features facilitate and speed up the movement of data into and out of the apparatus. “Hit” detection and histogram logic are also included.

Claims27

Dependent claims

An apparatus for processing data, comprising:

at least one processing element for processing data in response to processing element command words, wherein each of said at least one processing element includes processing resources coupled together to form a pipelined architecture having at least two stages;
and
a controller for receiving instructions and generating therefrom the processing element command words that are supplied to the at least one processing element, wherein the controller comprises:
means for converting each received instruction into a sequence of one or more first-type instructions having a first format that includes a first processing element stage field and a second processing element stage field, wherein the first processing element stage field specifies a first processing element stage operation to be performed during a first clock cycle, and the second processing element stage field specifies a second processing element stage operation to be performed during a second clock cycle that is subsequent to the first clock cycle;
and
means for converting the sequence of one or more first-type instructions into the sequence of processing element command words,
wherein:
each of the processing element command words has a second format that includes fields specifying first and second processing element stage operations that are to be performed during a same clock cycle;
each of said at least one processing element includes a synchronous random access memory (RAM) that requires application of a read address one clock cycle in advance of a clock cycle in which the contents of the addressed location in the synchronous RAM are needed at an output of the synchronous RAM;
and
the controller further includes means for detecting that one of the fields in a first-type instruction specifies that a synchronous RAM read operation is to be performed, and in response to said detection the controller supplies the read address to each of said at least one processing element one clock cycle in advance of a generated processing element control word that specifies the synchronous RAM read operation.

8 more elements

An apparatus for processing data, comprising:

a processing element array for processing data in response to processing element command words, wherein the processing element array comprises a plurality of identical processing elements, wherein:
each of the processing elements includes processing resources coupled together to form a pipelined architecture having at least two stages;
each of the processing elements is connected to at least one neighboring processing element;
and
each processing element is coupled to receive a same set of the processing element command words;
and
a controller for receiving instructions and generating therefrom the processing element command words that are supplied to the plurality of identical processing elements, wherein the controller comprises:
means for converting each received instruction into a sequence of one or more first-type instructions having a first format that includes a first processing element stage field and a second processing element stage field, wherein the first processing element stage field specifies a first processing element stage operation to be performed during a first clock cycle, and the second processing element stage field specifies a second processing element stage operation to be performed during a second clock cycle that is subsequent to the first clock cycle;
means for converting the sequence of one or more first-type instructions into the sequence of processing element command words, wherein each of the processing element command words has a second format that includes fields specifying first and second processing element stage operations that are to be performed during a same clock cycle;
and
means for receiving a non-zero skew amount associated with a first one of the first-type instructions, and in response thereto generating a skew-resolving sequence of processing element command words comprising:
a first processing element command word specifying a first processing element stage operation as specified by said first one of the first-type instructions;
and
one or more subsequent processing element command words specifying a first processing element stage operation that causes data to be received from a neighboring processing element.

11 more elements

A method of operating a data processing apparatus comprising at least one processing element for processing data in response to processing element command words, wherein each of said at least one processing element includes processing resources coupled together to form a pipelined architecture having at least two stages, and a synchronous random access memory (RAM) that requires application of a read address one clock cycle in advance of a clock cycle in which the contents of the addressed location in the synchronous RAM are needed at an output of the synchronous RAM;

and a controller for receiving instructions and generating therefrom the processing element command words that are supplied to the at least one processing element, the method comprising the steps of:
in the controller:
converting each received instruction into a sequence of one or more first-type instructions having a first format that includes a first processing element stage field and a second processing element stage field, wherein the first processing element stage field specifies a first processing element stage operation to be performed during a first clock cycle, and the second processing element stage field specifies a second processing element stage operation to be performed during a second clock cycle that is subsequent to the first clock cycle;
and
converting the sequence of one or more first-type instructions into the sequence of processing element command words,
wherein:
each of the processing element command words has a second format that includes fields specifying first and second processing element stage operations that are to be performed during a same clock cycle;
and
the controller further performs the step of detecting that one of the fields in a first-type instruction specifies that a synchronous RAM read operation is to be performed, and in response to said detection the controller supplies the read address to each of said at least one processing element one clock cycle in advance of a generated processing element control word that specifies the synchronous RAM read operation.

6 more elements

A method of operating a data processing apparatus comprising a processing element array for processing data in response to processing element command words, wherein the processing element array comprises a plurality of identical processing elements, wherein:

each of the processing elements includes processing resources coupled together to form a pipelined architecture having at least two stages;
each of the processing elements is connected to at least one neighboring processing element;
and each processing element is coupled to receive a same set of the processing element command words;
and a controller for receiving instructions and generating therefrom the processing element command words that are supplied to the plurality of identical processing elements, the method comprising the steps of:
in the controller:
converting each received instruction into a sequence of one or more first-type instructions having a first format that includes a first processing element stage field and a second processing element stage field, wherein the first processing element stage field specifies a first processing element stage operation to be performed during a first clock cycle, and the second processing element stage field specifies a second processing element stage operation to be performed during a second clock cycle that is subsequent to the first clock cycle;
converting the sequence of one or more first-type instructions into the sequence of processing element command words, wherein each of the processing element command words has a second format that includes fields specifying first and second processing element stage operations that are to be performed during a same clock cycle;
and
receiving a non-zero skew amount associated with a first one of the first-type instructions, and in response thereto generating a skew-resolving sequence of processing element command words comprising:
a first processing element command word specifying a first processing element stage operation as specified by said first one of the first-type instructions;
and
one or more subsequent processing element command words specifying a first processing element stage operation that causes data to be received from a neighboring processing element.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/057,481Filed 9 Apr 1998
Granted: 3 Apr 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 9/30014
Arithmetic instructions: with variable precision
G06F 9/30025
To perform operations on data operands: format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
G06F 9/30036
To perform operations on data operands: instructions to perform operations on packed data, e.g. vector, tile or matrix operations
G06F 9/30038
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations: using a mask