Universal dependency vector/queue entry

A method for scheduling instruction operations in a processor, the method comprising:

• generating a dependency vector corresponding to each instruction operation, said dependency vector indicating an arbitrary number of dependencies upon other instruction operations in an instruction queue and a second instruction queue, said dependency vector comprising an indication corresponding to each of a plurality of entries in said instruction queue and to each of a plurality of entries in said second instruction queue, wherein said indication, in a first state, is indicative of a dependency upon a corresponding entry from one of said plurality of queue entries or said second plurality of queue entries, and wherein said indication, in a second state, is indicative of a lack of dependency upon the corresponding entry;
• storing said dependency vector and a corresponding instruction operation in said instruction queue;
• satisfying each of said arbitrary number of dependencies indicated by said dependency vector;
• and
• scheduling said corresponding instruction operation responsive to said satisfying.

A computer system comprising:

• a processor comprising:
• a dependency vector generation unit configured to generate a dependency vector corresponding to an instruction operation;
• an instruction queue coupled to receive said dependency vector and said instruction operation, wherein said instruction queue is configured to inhibit scheduling of said instruction operation until each dependency indicated within said dependency vector is satisfied, and wherein said dependency vector is capable of indicating dependencies upon an, arbitrary number of other instruction operations within said instruction queue;
• and
• a second instruction queue coupled to said dependency factor generation unit and to said instruction queue, wherein said dependency vector comprises an indication corresponding to each of a plurality of queue entries within said instruction queue and to each of a second plurality of queue entries within said second instruction queue, and wherein said indication, in a first state, is indicative of a dependency upon a corresponding entry from one of said plurality of queue entries or said second plurality of queue entries, and wherein said indication, in a second state, is indicative of a lack of dependency upon the corresponding entry;
• and
• an input/output (I/O) device configured to communicate between said computer system and another computer system.