Method and system using tagged instructions to allow out-of-program-order instruction decoding

A microprocessor configured to decode instructions out of program order comprising:

• a cache;
• a first decoder coupled to said cache, wherein said first decoder is configured to receive and decode a first plurality of instruction bytes;
• and
• a second decoder coupled to said cache, wherein said second decoder is configured to receive a second plurality of instruction bytes from said cache, wherein said second decoder is configured to decode said second plurality of instruction bytes while said first decoder is decoding said first plurality of instruction bytes, wherein said second plurality of instruction bytes occur after said first plurality of instruction bytes in program order, and wherein said second decoder is configured to complete decoding said second plurality of instruction bytes before said first decoder is completed decoding said first plurality of instruction bytes;
• and
• wherein said first and second decoders are configured to generate tags corresponding to each decoded instruction, wherein said tags are indicative of program order.

A method for decoding instructions out of program order comprising:

• fetching a first group of instruction bytes from an instruction cache;
• assigning a first fetch tag to said first group;
• decoding said first group into a first number of instructions;
• assigning an instruction tag to each of said first number of instruction;
• issuing a particular instruction from said first number of instructions after all preceding instructions in program order have been decoded;
• fetching a second group of instruction bytes from said instruction cache;
• assigning a second fetch tag to said second group;
• decoding said second group into a second number of instructions before said first group is completed decoding;
• and
• assigning an instruction tag to each of said second number of instructions, wherein said second group occurs after said first group in program order.

A computer system comprising:

• a first microprocessor comprising:
• a cache configured to store a plurality of instruction bytes, wherein said cache is configured to receive a first fetch address and in response output a first group of bytes corresponding to said first fetch address;
• a tag generator coupled to said cache, wherein said tag generator is configured to generate a first fetch tag for said first group of instructions bytes;
• and
• a first decode unit coupled to said tag generator and said cache, wherein said first decode unit is configured to receive said first fetch tag and said first group of instruction bytes, wherein said first decode unit is configured to decode said first group of instruction bytes into one or more instructions, wherein said first decode unit is configured to generate an instruction tag for each instruction, and wherein said instruction tags are indicative of the program order of said one or more instructions;
• a CPU bus coupled to said microprocessor;
• and
• a modem coupled to CPU bus via a bus bridge.