Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals

A single-chip microcomputer operable in a slave mode or a master mode in accordance with a mode selection signal supplied from outside of the microcomputer, the microcomputer comprising:

• a central processing unit;
• a serial communication unit which is coupled to an internal bus and which controls the communication of serial data to and from outside of the microcomputer;
• data terminals to be externally coupled to an external data bus;
• a first terminal operable for outputting a bus request signal representing a request of a right to use the external data bus by the microcomputer when the microcomputer operates in the slave mode;
• a second terminal operable for inputting a bus acknowledge signal representing an acknowledgement of the right to use the external data bus by the microcomputer when the microcomputer operates in the slave mode;
• and
• a bus controller coupled to the data terminals, the first terminal and the second terminal and responsive to the mode selection signal and controlling functions of the first and second terminals so that the first terminal is operable for outputting a bus grant signal representing a grant of the right to use the external data bus by the microcomputer and the second terminal is operable for inputting a bus by the microcomputer release signal representing a request of the right to use the external data bus when the microcomputer operates in the master mode;
• and
• wherein the internal bus is coupled to the central processing unit, the serial communication unit and the bus controller.

A single-chip microcomputer operable in a master mode or a slave mode, the microcomputer comprising:

• a central processing unit;
• an internal bus coupled to the central processing unit;
• data terminals to be externally coupled to an external data bus;
• a mode terminal to be externally supplied with a first level of a mode signal indicating that the microcomputer operates in the master mode or a second level of the mode signal indicating that the microcomputer operates in the slave mode;
• a first terminal for outputting a bus request signal indicating a request for a right to use the external data bus by the microcomputer when the microcomputer is operating in the slave mode and a bus grant signal indicating a grant of the right to use the external bus by the microcomputer when the microcomputer is operating in the master mode;
• a second terminal for inputting a bus acknowledge signal indicating an acknowledgement of the right to use the external data bus by the microcomputer when the microcomputer is operating in the slave mode and a bus release signal indicating a request of the right to use the external data bus by the microcomputer when the microcomputer is operating in the master mode;
• and
• a bus controller coupled to the mode terminal, the first terminal and the second terminal and responsive to the mode signal for controlling functions of the first terminal and the second terminal.

A single-chip microcomputer operable in a slave mode or a master mode, comprising:

• a central processing unit;
• an internal bus coupled to the central processing unit;
• a data bus interface coupled to the internal bus and including a plurality of data terminals to be externally coupled to an external data bus;
• first and second bus access/control terminals;
• and
• a bus use priority controller coupled to the first and second bus access/control terminals for controlling the use of the external data bus, wherein the bus use priority controller operates responsive to an externally supplied mode signal indicating whether the microcomputer is operating in the slave mode or the master mode;
• wherein the bus use priority controller controls signaling on the first and second access/control terminals,
• wherein the first access/control terminal is controlled to output a bus request signal representing a request of a right to use the external data bus by the microcomputer and the second access/control terminal is controlled to input a bus acknowledge signal representing a grant of the right to use the external data bus by the microcomputer when the microcomputer operates in the slave mode, and
• wherein the first access/control terminal is controlled to output a bus grant signal representing a grant of the right to use the external data bus by the microcomputer and the second access/control terminal is controlled to input a bus release signal representing a request of the right to use the external bus by the microcomputer when the microcomputer operates in the master mode.