System and method for high-speed register renaming by counting

A superscalar computer architecture for executing instructions out-of-order with at least several instructions performing computations on data in computer architected registers, comprising:

• a source of instructions which are arranged in an order that the instructions are to be executed;
• a multiplicity of execution units for executing the instructions;
• a plurality of physical registers for storing data;
• means for mapping source and target architected registers in the instructions into said physical registers;
• and
• means for generating a list of tags corresponding to physical registers that are not in use during mapping of said source and target architected registers, said generating means including means for constructing a table having one bit for each phvsical register per instruction in flight.

A data processing system comprising:

• memory means for storing data;
• a bus communicating with said memory means;
• and
• at least one processing unit communicating with said bus, wherein said processing unit has
• a multiplicity of pipelined execution units for executing instructions contained in said data,
• a plurality of general-purpose registers for storing data,
• means for mapping source and target architected registers in the instructions into said general-purpose registers,
• means for generating a list of tags corresponding to general-purpose registers that are not in use during mapping of said source and target architected registers, including means for constructing a table having one bit for each general-purpose register per instruction in flight, wherein said mapping means uses said vector to supply tags of said general-purpose registers that may be assigned as targets, and to supply validity bits for said tags.