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US 6,212,614 B1Granted
Legacy MIL-STD-1750A software emulator address translation using power PC memory management hardware
AssigneeTRW Inc.
InventorsTimothy R. Hoerig, William J. Cannon
Life of this patent
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Abstract
A system and method for implementing the paging and protection attributes, such as block protection and access lock and key functions promulgated in MIL-STD-1750A. The present invention takes advantage of the PowerPC microprocessor architecture to implement the paging and protection attributes required by MIL-STD-1750A in hardware. Since the paging and the protection attributes are implemented in hardware, the system performance is greatly improved.
Claims11
A memory system comprising:
- one or more logical page registers, at least one of said logical page register configured to map 64K bytes of logical address space to sixteen (16) 4K word logical pages on 4K word boundaries;
- and
- means for mapping each of said 4K word logical pages to four (4) 4K byte physical address pages, wherein each word in logical address space is mapped to 4 bytes in said physical address space;
- wherein said mapping means implemented in hardware.
1 more element
A method for mapping logical address space to physical memory space, the method comprising the steps of:
- (a) providing one or more logical page registers configured to map 64K words of logical address space to sixteen (16) 4K word logical pages on 4K word logical pages on 4K word boundaries;
- and
- (b) mapping each of said 4K word logical pages to four (4) 4K byte physical address pages, wherein each word in logical address space is mapped to 4 bytes in said address pages.
Dependencies are inferred from the claim text.