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US 6,212,611 B1Granted
Method and apparatus for providing a pipelined memory controller
AssigneeIntel Corporation
InventorsPuthiya K. Nizar, Michael W. Williams
Life of this patent
Estimating the term…
Abstract
A pipelined memory controller that includes a decode stage, and a schedule stage, wherein the schedule stage includes a command queue to store multiple commands. In one embodiment, the schedule stage further includes look ahead logic which can modify an order memory commands are stored in the command queue.
Claims23
A pipelined memory controller comprising:
- a decode stage;
- and
- a scheduling stage coupled to said decode stage, said scheduling stage including a command queue to store multiple commands and Look Ahead Logic that modifies an order memory commands are stored in said command queue.
A pipelined memory controller comprising:
- means for decoding a memory request;
- and
- means for scheduling multiple memory commands into a command queue for storing multiple memory commands, said means for scheduling multiple memory commands includes Look Ahead Logic that includes means for modifying an order memory commands are stored in said command queue.
A pipelined memory controller comprising:
- a decode stage;
- and
- a scheduling stage coupled to said decode stage, said scheduling stage including two command queues to store multiple commands, and look ahead logic to modify an order commands are stored in said command queues.
Dependencies are inferred from the claim text.