US 6,212,607 B1 · Multi-ported memory architecture using single-ported RAM

Abstract

A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0˜401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0˜405-7, 406-0˜406-7, 407-0˜407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L˜2500-3L, 2500-0R˜2500-3R), interrupt generating circuitry (2514-0L˜2514-3L, 2514-0R˜2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L˜3102L, 3101R˜3102R, 3301L˜3302L, 3301R˜3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.

Claims26

Dependent claims

A multi-ported memory device having at least two input/output ports, comprising:

a plurality of single-ported memory banks individually having a plurality of addressable memory cells;
means for receiving bank access request signals through said at least two input/output ports for selected ones of said plurality of single-ported memory banks, and granting exclusive access through individual ones of said at least two input/output ports to individual ones of said selected single-ported memory banks on a first received access request basis;
and
at least one first mail-box register dedicated to storing data received through a first one of said at least two input/output ports, and transmitted through a second one of said at least two input/output ports.

1 more element

A multi-ported memory device having at least two input/output ports, comprising:

a plurality of single-ported memory banks individually having a plurality of addressable memory cells;
means for receiving bank access request signals through said at least two input/output ports for selected ones of said plurality of single-ported memory banks, and granting exclusive access through individual ones of said at least two input/output ports to individual ones of said selected single-ported memory banks on a first received access request basis;
coupling means for coupling said exclusive access granted single-ported memory banks to said individual ones of said single-ported memory banks;
and
at least one first mail-box register dedicated to storing data received through a first one of said at least two input/output ports, and transmitted through a second one of said at least two input/output ports, wherein said first one of said input/output ports includes a first address bus having a first plurality of address lines for communicating to said coupling means, memory bank addresses indicative of selected ones of said plurality of single-ported memory banks when a first control signal is in a first mode, and a second plurality of address lines for communicating memory cell addresses indicative of selected ones of said plurality of addressable memory cells of said selected single-ported memory banks when said first control signal is in said first mode.

2 more elements

Dependencies are inferred from the claim text.

Multi-ported memory architecture using single-ported RAM

Life of this patent

Multi-ported memory architecture using single-ported RAM

Life of this patent

Abstract

Claims26