Shared instruction cache for multiple processors
AssigneeSun Microsystems, Inc.
InventorMarc Tremblay
Life of this patent
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Abstract
The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).
Claims22
An apparatus for a microprocessor, comprising:
- a shared instruction cache, the shared instruction cache being shared by a first processor and a second processor of the microprocessor;
- and
- a first register index base coupled to the first processor, and
- a second register index base coupled to the second processor,
- wherein the first register index base and the second register index base enable a single instruction stored in the shared instruction cache to be executed on both the first processor and the second processor.
A method for a shared instruction cache of a microprocessor, comprising:
- storing an instruction in an instruction cache, the instruction cache being shared by a first processor and a second processor of the microprocessor;
- storing a first register index base for the first processor;
- storing a second register index base for the second processor;
- and,
- using the first register index base and the second register index base to enable the instruction to be executed on both the first processor and the second processor.
An apparatus for a shared instruction cache, comprising:
- an instruction cache, the instruction cache storing an instruction that can be executed by a first processor and by a second processor;
- a first register index base for the first processor stored in a first register;
- and
- a second register index base for the second processor stored in a second register.
Dependencies are inferred from the claim text.