Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory

A data processor comprising:

• a L0 cache;
• a L1 cache;
• an execution core;
• logic that disperses instructions to the execution core;
• instruction fetch pipeline to fetch the instructions;
• a branch prediction pipeline that makes predictions for branches;
• an instruction prefetch pipeline to prefetch instructions into the L0 cache, the instruction prefetch pipeline receiving prefetch requests from the branch prediction pipeline;
• an address translation pipeline to translate virtual addresses associated with the instructions into physical addresses;
• wherein the instruction fetch, address translation, and branch prediction pipelines have associated first, second, and third pipeline stages, the first pipeline stage generating an instruction fetch address, the second pipeline stage fetching the instructions from the L0 cache, translating the virtual addresses, and making branch predictions, and the third pipeline stage dispersing the instructions to the execution core;
• the data processor further comprising:
• an instruction streaming buffer (ISB) that stores an instruction of a miss request returned from the L1 cache before the instruction is written into the L0 cache;
• a bypass path that provides the instruction from a plurality of bypass sources other than the L0 cache before the instruction is written into the instruction cache responsive to a demand request, the bypass sources including the ISB;
• and
• a request address buffer (RAB) that registers the virtual and physical addresses associated with the instruction, each entry of the RAB having an identification (ID) that is sent to the L1 cache as part of the miss request along with an indicator that determines fetch priority of the miss request, the ID being returned to the RAB from the L1 cache to read out the virtual and physical addresses corresponding to the instruction of the miss request, the virtual and physical addresses being read out from the RAB into the ISB.

Apparatus for prefetching operations in a processor with associated L0 and L1 caches, the apparatus comprising:

• an instruction streaming buffer (ISB) that stores an instruction of a miss request returned from the L1 cache before the instruction is written into the L0 cache;
• a bypass path that provides the instruction from a plurality of bypass sources other than the L0 cache before the instruction is written into the instruction cache responsive to a demand request, the bypass sources including the ISB;
• and
• a request address buffer (RAB) that registers the virtual and physical addresses associated with the instruction, each entry of the RAB having an identification (ID) that is sent to the L1 cache as part of the miss request along with an indicator that determines fetch priority of the miss request, the ID being returned to the RAB from the L1 cache to read out the virtual and physical addresses corresponding to the instruction of the miss request, the virtual and physical addresses being read out from the RAB into the ISB.