Microprocessor system with block move circuit disposed between cache circuits

A single integrated circuit microprocessor, comprising:

• an instruction pipeline, wherein said instruction pipeline comprises an execution stage operable to process a an information unit of a first length;
• a cache circuit comprising a memory operable to store a transfer unit of information of a second length and accessible by said instruction pipeline, wherein said second length is greater than said first length;
• a block move circuit coupled to said cache circuit and operable to read/write a transfer unit of information of said second length into said memory of said second cache circuit;
• wherein said cache circuit comprises a first cache circuit;
• further comprising a second cache circuit accessible by said instruction pipeline, wherein said first cache circuit is accessed in response to a miss in said second cache circuit;
• and
• wherein a transfer unit of information to be read and written by said block move circuit has a corresponding address;
• and further comprising:
• determining circuitry for determining whether said second cache stores a dirty copy of said transfer unit of information to be read and written by said block move circuit at said corresponding address prior to said block move circuit reading said transfer unit of information;
• and
• circuitry for writing said transfer unit of information from said second cache circuit to said first cache circuit prior to said block move circuit writing said transfer unit of information in response to said determining circuitry determining that said second cache stores a dirty copy of said transfer unit of information.

A single integrated circuit microprocessor, comprising:

• an instruction pipeline, wherein said instruction pipeline comprises an execution stage operable to process an information unit of a first length;
• a first cache circuit comprising a memory operable to store a transfer unit of information of a second length and accessible by said instruction pipeline, wherein said second length is greater than said first length;
• a second cache circuit accessible by said instruction pipeline, wherein said first cache circuit is accessed in response to a miss in said second cache circuit;
• a block move circuit coupled to said cache circuit and operable to read/write a transfer unit of information of said second length into said memory of said second cache circuit;
• wherein said memory of said cache circuit comprises a number of storage areas, wherein each of said storage areas comprises a set of outputs, and wherein a set of outputs for each of said storage areas is physically ordered in an integer number of interleaved positions with respect to said sets of outputs of all other of said storage areas;
• and
• wherein said block move circuit comprises a plurality of rotate circuits;
• and
• wherein each of said plurality of rotate circuits is operable to receive and rotate a number of bits equal to said integer number.

A single integrated circuit microprocessor, comprising:

• an instruction pipeline, wherein said instruction pipeline comprises an execution stage operable to process an information unit of a first length;
• a first cache circuit comprising a memory operable to store a transfer unit of information of a second length and accessible by said instruction pipeline, wherein said second length is greater than said first length;
• a second cache circuit accessible by said instruction pipeline, wherein said first cache circuit is accessed in response to a miss in said second cache circuit;
• a block move circuit coupled to said cache circuit and operable to read/write a transfer unit of information of said second length into said memory of said second cache circuit;
• wherein said memory of said cache circuit comprises a number of storage areas, wherein each of said storage areas comprises a set of outputs, and wherein a set of outputs for each of said storage areas is physically ordered in an integer number of interleaved positions with respect to said sets of outputs of all other of said storage areas;
• and
• wherein a transfer unit of information to be read and written by said block move circuit has a corresponding address;
• and further comprising:
• determining circuitry for determining whether said second cache stores a dirty copy of said transfer unit of information to be read and written by said block move circuit at said corresponding address prior to said block move circuit reading said transfer unit of information;
• and
• circuitry for writing said transfer unit of information from said second cache circuit to said first cache circuit prior to said block move circuit writing said transfer unit of information in response to said determining circuitry determining that said second cache stores a dirty copy of said transfer unit of information.

A single integrated circuit microprocessor, comprising:

• an instruction pipeline, wherein said instruction pipeline comprises an execution stage operable to process an information unit of a first length;
• a first cache circuit comprising a memory operable to store a transfer unit of information of a second length and accessible by said instruction pipeline, wherein said second length is greater than said first length;
• a second cache circuit accessible by said instruction pipeline, wherein said first cache circuit is accessed in response to a miss in said second cache circuit;
• a block move circuit coupled to said cache circuit and operable to read/write a transfer unit of information of said second length into said memory of said second cache circuit;
• wherein said memory of said cache circuit comprises a number of storage areas, wherein each of said storage areas comprises a set of outputs, and wherein a set of outputs for each of said storage areas is physically ordered in an integer number of interleaved positions with respect to said sets of outputs of all other of said storage areas;
• and
• wherein a transfer unit of information to be read and written by said block move circuit has a corresponding address;
• and further comprising:
• determining circuitry for determining whether said second cache stores a copy of said transfer unit of information to be written by said block move circuit at said corresponding address;
• and
• circuitry for invalidating said copy of said transfer unit of information at said corresponding address prior to said block move circuit writing said transfer unit of information in response to said determining circuitry determining that said second cache stores a copy of said transfer unit of information at said corresponding address.

A single integrated circuit microprocessor, comprising:

• an instruction pipeline, wherein said instruction pipeline comprises an execution stage operable to process an information unit of a first length;
• a cache circuit comprising a memory operable to store a transfer unit of information of a second length and accessible by said instruction pipeline, wherein said second length is greater than said first length;
• a block move circuit coupled to said cache circuit and operable to read/write a transfer unit of information of said second length into said memory of said second cache circuit;
• wherein said memory of said cache circuit comprises a number of storage areas, wherein each of said storage areas comprises a set of outputs, and wherein a set of outputs for each of said storage areas is physically ordered in an integer number of interleaved positions with respect to said sets of outputs of all other of said storage areas, such that the number of storage areas defines the number of bits output as a group, wherein said group comprises a single bit from each of said storage areas and wherein further said second length divided by said number of storage areas defines the number of groups of bits in a single write cycle;
• and
• wherein further said groups of bits output in a single write cycle represent one transfer unit of information and are processed simultaneously and according to the steps of:
• rotating said bits in each of said groups from zero to said integer number of bit positions right, via a rotate circuit, in response to a rotate control signal from said execution stage;
• latching said rotated bits or passing said rotated bits through in a particular pattern in response to a merge mask signal from said execution stage;
• providing a next group of bits representing the next addressed transfer unit of information to a second latch circuit for latching said bits in response to a second control signal from said execution stage;
• rotating said next group of latched bits the same number of bit positions as said previously group of bits, via said rotate circuit;
• latching said rotated bits of passing said rotated bits through in exactly the inverse of said particular pattern;
• and
• writing said bits remaining in said latches post said latching and passing through into said cache circuit.