Method and apparatus for a memory control system including a secondary controller for DRAM refresh during sleep mode

A memory control system comprising:

• a dynamic random access memory (DRAM) including synchronous dynamic random access memory (SDRAM);
• a first memory controller for controlling the DRAM during a first operation mode, the first memory controller including a first power connection;
• and
• a second memory controller designed to maintain the DRAM during a second operation mode, the second memory controller including a second power connection, the second memory controller generating:
• a first signal to indicate to the first memory controller that the second memory controller is controlling the DRAM;
• a second signal to maintain the SDRAM in a self-refresh mode;
• and
• a third signal to indicate to the first controller an exit from the second operation mode, such that the first memory controller need not be initialized in order to receive control from the second memory controller;
• wherein the first power connection may be disconnected during the second operation mode, such that the second memory controller remains powered by the second power connection and maintains the DRAM.

A memory control system comprising:

• a first memory controller designed to access and refresh a DRAM, using a clock, during a first operation mode;
• a second memory controller designed to maintain the DRAM during a second operation mode and to exit the first memory controller from the second operation mode, wherein the second memory controller is further designed to receive a bank population signal, indicating memory banks of the DRAM which are occupied by a first type of DRAM, and wherein only those memory banks of the DRAM that are occupied by the first type of DRAM are refreshed;
• and
• a first power connection removed from the first memory controller during the second operation mode, wherein the first memory controller, upon exit from the second operation mode, is not reset and takes over control from the second memory controller.