Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like
AssigneeNeoNet LLLC
InventorsRichard Conlin, Tim Wright, Peter Marconi, Mukesh Chatter
Life of this patent
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Abstract
Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.
Claims38
In a multi-port internally cached array of AMPIC DRAM units in which a plurality of system I/O resources interface along common internal data buses connected to corresponding DRAM cores in each unit of the array, and wherein data from a CPU or similar source may also be transferred with each unit along the buses during data transfer cycles, the method of improving performance, that comprises, concurrently with the data transfer, enabling the system I/O resources to send multi-bit messages to one another by sending the message from one system I/O resource, intended for a system destination I/O resource, to the AMPIC DRAM units which, upon receiving the message data, choose a free address location in the DRAM array and write the message to that location, so informing the system destination I/O resource with a message ready signal;
- and, when the system destination I/O resource is ready to accept the message, retrieving its portion of the message data from each DRAM of the array and forwarding the data on to the destination I/O resources, all independently of the internal structure of the AMPIC DRAM units, and with the array functioning as a store and forward cross-connect array.
In a multi-port internally cached array of AMPIC DRAM units in which a plurality of system I/O resources interface along common internal data buses connected to corresponding DRAM cores in each unit of the array, and wherein data from a processing source may also be transferred with each unit along the buses during data transfer cycles, the method of improving performance, that comprises, concurrently with the data transfer, enabling the system I/O resources to send multi-bit messages to one another by sending the message from one system I/O resource to all AMPIC DRAM units of the array during said data transfer cycles, and concurrently with bit information on message address location in the DRAM wherein the AMPIC DRAM array is divided into several independently controlled banks greater than or equal to the number of system I/O resources connected to the AMPIC DRAM, and each internal data bus is divided evenly between each of the DRAM banks, and wherein each system I/O resource is converted to a data port within the AMPIC DRAM, and the step is performed of dividing each port into a number of slots equal to the number of DRAM banks, and streaming data arriving from the system I/O resource into the appropriate slot of that system I/O resource data port as determined by the DRAM address to which the data is to be written, and in turn determining into which DRAM bank the data is written.
Apparatus for enhancing the performance of a multi-port internally cached (AMPIC) array of DRAM units in which a plurality of system I/O resources interface along common internal data buses connected to corresponding DRAM cores in each unit of the array, and wherein data from a processing source may also be transferred with each unit along the buses during data transfer cycles, said apparatus having, in combination, logic circuits for enabling the system I/O resources to send multi-bit messages to one another by sending the message from one system I/O resource to all AMPIC DRAM units of the array during said data transfer cycles, and concurrently with the information on message address location in the DRAM;
- each AMPIC DRAM unit receiving a different portion of the data during said transfer, and with each AMPIC DRAM unit connected to receive the same DRAM message address location and to write the message transmitted by a system I/O resource into the same location in the internal DRAM array, wherein destination system I/O resources are provided with means for enabling the message to be read out, and wherein the array is divided into several independently controlled DRAM banks in which each system I/O resource is connected to a data port within the AMPIC DRAM, and each port is divided into a number of slots equal to the number of DRAM banks, with data arriving from the system I/O resource streaming into the appropriate slot of that system I/O resource data port as determined by the DRAM address to which the data is to be written, and in turn determining into which DRAM bank the data is written.
Dependencies are inferred from the claim text.