US 6,212,596 B1 · Synchronous memory and data processing system having a programmable burst length

Abstract

A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to with a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). A number of data bits corresponding to a control signal such as a wrap length (WL) signal are read out from the memory in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Claims20

Dependent claims

A synchronous memory, comprising:

a memory array arranged in rows and columns of memory cells, each memory cell arranged to store a respective data bit;
a control circuit coupled to receive a system clock signal and a binary select signal, the control circuit arranged to produce a control signal;
a row address circuit arranged to latch a row address signal in response to the system clock signal and the binary select signal, the row address circuit arranged to select at least one row from the rows of memory cells;
and
a column address circuit arranged to latch a column address signal in response to the system clock signal and the binary select signal, the column address circuit arranged to produce a number of column address signals corresponding to the control signal, wherein the column address signals are produced in synchronization with the system clock signal, and wherein each column address signal corresponds to at least one column of memory cells from the columns of memory cells.

2 more elements

A data processing system, comprising:

a clock circuit arranged to produce a system clock signal;
a digital processor coupled to the clock circuit and arranged to operate synchronously with the system clock signal;
a synchronous memory coupled to the digital processor and the clock circuit and arranged to operate synchronously with the system clock signal, the synchronous memory comprising:
a memory array arranged in rows and columns of memory cells, each memory cell arranged to store a respective data bit;
a control circuit coupled to receive the system clock signal and a select signal, the control circuit arranged to produce a control signal;
a row address circuit arranged to latch a row address signal in response to the system clock signal and the select signal, the row address circuit arranged to select at least one row from the rows of memory cells;
and
a column address circuit arranged to latch a column address signal in response to the system clock signal and the select signal, the column address circuit arranged to produce a number of column address signals corresponding to the control signal, wherein the column address signals are produced in synchronization with the system clock signal, and wherein each column address signal corresponds to at least one column of memory cells from the columns of memory cells.

5 more elements

Dependencies are inferred from the claim text.

Synchronous memory and data processing system having a programmable burst length

Life of this patent

Synchronous memory and data processing system having a programmable burst length

Life of this patent

Abstract

Claims20