Timer with fixed and programmable interrupt periods

A method for causing two programmable interrupts to take place, using a counter having an output and an adjustable period, a first register which controls the length of the total period of the counter, a second register which controls the length of the second portion of the period of the counter cycle, the steps in the method comprising:

• loading a first register with a first value;
• loading a second register with a second value which is less than said first value;
• simultaneously causing a counter to count down from said first value to zero, and causing an output representing a first interrupt signal of a timer to be a binary “1” during a first portion of the counter period;
• comparing the value of said first register to the value of said second register;
• and
• causing, said output representing a second interrupt signal of said counter to be a binary “0”, when the value of said first register and said second register are equal and until the value of said first register becomes zero.

A method for causing two programmable interrupt to take place, using a counter having an output and an adjustable period, a first register which controls the length of the total period of the counter, a second register which controls the length of the second portion of the period of the counter cycle, the steps in the method comprising:

• loading a first register with a first value;
• loading a second register with a second value which is less than said first value;
• simultaneously causing a counter to count down from said first value to zero, and causing an output representing a first interrupt signal of a timer to be a binary “0” during a first portion of the counter period;
• comparing the value of said first register to the value of said second register;
• and
• causing, said output representing a second interrupt signal of said counter to be a binary “1”, when the value of said first register and said second register are equal and until the value of said first register becomes zero.

A method for causing two programmable interrupts to take place, using a counter having an output and an adjustable period, a first register which controls the length of the total period of the counter, a second register which controls the length of the second portion of the period of the counter cycle, the steps in the method comprising:

• loading a first register with a first value;
• loading a second register with a second value which is less than said first value;
• simultaneously causing a counter to count up from a value of zero to said first value, and causing an output representing a first interrupt signal of a timer to be binary “1” during a first portion of the counter period;
• comparing the value of said first register to the value of said second register;
• and
• causing, said output representing a second interrupt signal of said counter to be a binary “0”, when the value of said first register and said second register are equal and until the value of said first register becomes zero.

An apparatus for providing two programmable interrupts comprising:

• a counter having a first input, a second input, and an output;
• a first register coupled to said first input of said counter, the contents of said first register, at the beginning of a period of said counter, determining the period of the next cycle of said counter;
• a second register coupled to said second input of said counter, the contents of said second register, at the beginning of a period of said counter, determining the duration of the second portion of said next cycle of said counter output;
• and
• wherein the output representing a first interrupt signal of said counter is high during a first portion of said period of said counter, and wherein said output representing a second interrupt signal is low during said second portion of said counter.

An apparatus for providing two programmable interrupts comprising:

• a counter having a first input, a second input, and an output;
• a first register coupled to said first input of said counter, the contents of said first register, at the beginning of a period of said counter, determining the period of the next cycle of said counter;
• a second register coupled to said second input of said counter, the contents of said second register, at the beginning of a period of said counter, determining the duration of the second portion of said next cycle of said counter output;
• and
• wherein the output of said counter representing a first interrupt signal is low during a first portion of said period of said counter, and wherein said output representing a second interrupt signal high during said second portion of said counter.