US 6,212,592 B1Granted

Computer system for processing system management interrupt requests

AssigneeMicron Technology, Inc.

InventorDean A. Klein

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Abstract

A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced without waiting for lower priority system management interrupts to be serviced completely. In particular, the system executes a first SMI handler routine in response to receiving a first SMI from a first SM requester. In response to receiving a second SMI asserted by a second SM requester, the system determines whether the second SMI request has been assigned a higher priority than the first SMI request. If so, then the system interrupts executing the first SMI handler routine and executes a second SMI handler routine corresponding to the second SMI request. Otherwise, the system completes executing the first SMI handler routine and then executes the second SMI handler routine.

Claims17

Dependent claims

A computer system for processing system management interrupt (SMI) requests, comprising:

a first system management (SM) requester that asserts SMI requests;
a second SM requester that asserts SMI requests;
a processor coupled to the first and second SM requesters, the processor activating a system management mode in response to receiving an SMI request from one of the SM requesters;
a system memory;
a memory controller coupled to the processor and the system memory, the memory controller accessing a first SMI handler routine in the system memory if the processor activates system management mode in response to receiving an SMI request from the first SM requester and accessing a second SMI handler routine in the system memory if the processor activates system management mode in response to receiving an SMI request from the second SM requester, the memory controller including
a first SMI base address register that stores a first SMI base address corresponding to the first SMI handler routine;
a second SMI base address register that stores a second SMI base address corresponding to the second SMI handler routine;
a memory address register block that stores an address of information that is accessed from the system memory;
first and second multiplexers, the first multiplexer having a first input coupled to the first SMI base address register, a second input coupled to the second SMI base address register, and an output coupled to a first input of the second multiplexer, the second multiplexer having a second input coupled to the processor, and an output coupled to the memory address register block;
and
an SMI state machine coupled to the processor, the first multiplexer, and the SMI base address registers, the SMI state machine causing the first multiplexer to transmit the first SMI base address to the second multiplexer in response to receiving from the processor an indication that the processor received an SMI request from the first SMI requester and causing the first multiplexer to transmit the second SMI base address to the second multiplexer in response to receiving from the processor an indication that the processor received an SMI request from the second SMI requester, the SMI state machine further causing the second multiplexer to load into the memory address register block whichever SMI base address is output by the first multiplexer when the computer system is in system management mode and allowing the second multiplexer to load into the memory address register block an address from the processor when the computer system is not in system management mode.

8 more elements

A computer system for processing system management interrupt (SMI) requests, comprising:

a first SM requester that asserts a first system management interrupt (SMI) request;
executing means for executing a first SMI handler routine in response to receiving the first SMI request;
a second SM requester that asserts a second SMI request;
and
control means for interrupting execution of the first SMI handler routine in response to receiving the second SMI, wherein the executing means includes means for executing a second SMI handler routine in response to receiving the second SMI, the control means including a multiplexer that receives an SMI base address from an SMI base address register, a mode indicator signal from the executing means, and a context address from the executing means, and outputs either the SMI base address when the mode indicator signal indicates the executing means is in a system management mode or the context address when the mode indicator signal indicates the executing means is not in the system management mode.

2 more elements

A memory controller for a computer system for processing system management interrupt (SMI) requests, the computer system including a system memory, processor, and plural system management (SM) requesters, the memory controller comprising:

a first SMI base address register that stores a first SMI base address corresponding to a first SMI handler routine;
a second SMI base address register that stores a second SMI base address corresponding to a second SMI handler routine;
an SMI state machine coupled to the SMI base address registers, the SMI state machine being able to retrieve the first SMI base address from the first SMI base address register in response to receiving an indication that the processor received an SMI request from the first SMI requester and being able to retrieve the second SMI base address from the second SMI base address register in response to receiving an indication that the processor received an SMI request from the second SMI requester;
and
a selector component operatively coupled to the SMI state machine and the processor, the selector component receiving the first or second SMI base address from the SMI state machine, a mode indicator signal from the processor, and a context address from the processor, and outputting the first or second SMI base address when the mode indicator signal indicates the processor is in a system management mode, or outputting the context address when the mode indicator signal indicates the processor is not in the system management mode.

2 more elements

Dependencies are inferred from the claim text.