System resource arbitration mechanism for a host bridge
AssigneeIntel Corporation
InventorsGeorge Hayek, Brian Langendorf, Aniruddha Kundu, Gary Solomon, Peter D. MacWilliams, James M. Dodd
Life of this patent
Estimating the term…
Abstract
A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.
Claims21
A method for arbitrating access to a system resource in a computer system having a CPU coupled to a host bus and a set of bus agents coupled to a peripheral bus, the method comprising:
- defining a first priority scheme for requests to access the system resource and the peripheral bus via the host bus and a second priority scheme for requests to access the system resource via the peripheral bus;
- arbitrating between a host bus request and a peripheral bus request to designate a first priority request and a second priority request based upon the first priority scheme and the second priority scheme;
- and
- providing access to the system resource for the first priority request while processing any one of the second priority request, a host bus request to access the peripheral bus, and a transaction between at least two of the bus agents.
A computer system, comprising:
- a CPU;
- a set of bus agents;
- a host bus coupled to the CPU;
- a peripheral bus coupled to the set of bus agents;
- a system resource;
- and
- a host bridge coupled to the host bus, the peripheral bus and the system resource, said host bridge comprising an arbiter to designate a first priority request and a second priority request between a request to access either the system resource or the peripheral bus via the host bus and a request to access the system resource via the peripheral bus based upon a first priority scheme for host bus requests and a second priority scheme for peripheral bus requests, and to provide access to the system resource for the first priority request while processing any one of the second priority request, a host bus request to access the peripheral bus, and a transaction between at least two of the bus agents.
An arbiter for a system resource in a computer system having a CPU coupled to a host bus and a set of bus agents coupled to a peripheral bus, said arbiter designating a first priority request and a second priority request between a request to access either the system resource or the peripheral bus via the host bus and a request to access the system resource via the peripheral bus based upon a first priority scheme for host bus requests and a second priority scheme for peripheral bus requests, and providing access to the system resource for the first priority request while processing any one of the second priority request, a host bus request to access the peripheral bus, and a transaction between at least two of the bus agents.
Dependencies are inferred from the claim text.