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US 6,212,543 B1Granted
Asymmetric write-only message queuing architecture
AssigneeIntel Corporation
InventorWilliam T. Futral
Life of this patent
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AssigneeIntel Corporation
InventorWilliam T. Futral
Estimating the term…
A method and apparatus for write-only message queuing that allows messages to be passed between devices in a system through use of write operations only. Because the present invention passes information between devices using write operations rather than read operations information can be passed more efficiently than use of both read and write operations to pass the same information. Conceptually, the present invention provides a queue that stores indicators of work to be processed (e.g., data, pointers to data). The queue also has free space that can be used to store newly arriving work to be processed. A device producing work to be stored in the queue (producer) stores indications of one or more of: the start of free space (free space head pointer), the top of work to be processed (work list head pointer) and the end of the free space (free space tail pointer). A device processing work in the queue (consumer) stores indications of one or more of: the end of work to be processed (work list tail pointer), the beginning of work to be processed (future work pointer), and the beginning of work processed (work pointer). Changes to pointers in either the producer or the consumer are written to the counterpart device so that pointer information is available without performing a read operation of the other device.
A method for message queuing comprising:
An apparatus for message queuing comprising:
A system comprising:
A method of message queuing comprising:
Dependencies are inferred from the claim text.