Method for the performance of an integer division with a modular arithmetic coprocessor
AssigneeSTMicroelectronics S.r.l.
InventorBernard Plessier
Life of this patent
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Abstract
A division method and division circuit that can be integrated into a modular arithmetic coprocessor performs a reversal by word for the dividend and the quotient. This is done using a plurality of registers.
Claims30
A method for implementing an integer division in a modular arithmetic coprocessor, the division relating to a dividend A, encoded on α words of Bt bits, divided by a divider N, encoded on n words of Bt bits, to obtain a quotient S, encoded on α−n+1 words of Bt bits, the method comprising the steps of:
- entering at least one word of Bt bits of the dividend A bit-by-bit into a dividend shift register in a first order;
- and
- outputting the at least one word of Bt bits of the dividend A from the dividend shift register bit-by-bit in an order that is a reverse of the first order.
A method for implementing an integer division in a modular arithmetic coprocessor, the division relating to a dividend A, encoded on α words of Bt bits, divided by a divider N, encoded on n words of Bt bits, to obtain a quotient S, encoded on α−n+1 words of Bt bits, the method comprising the steps of:
- entering at least one word of Bt bits of the quotient S bit-by-bit into a quotient shift register in a first order;
- and
- outputting the at least one word of Bt bits of the quotient S from the quotient shift register bit-by-bit in an order that is a reverse of the first order.
A method for implementing an integer division in a modular arithmetic coprocessor, the division relating to a dividend A, encoded on α words of Bt bits, divided by a divider N, encoded on n words of Bt bits, to obtain a quotient S, encoded on α−n+1 words of Bt bits, the method comprising the steps of:
- entering at least one word of Bt bits of the dividend A bit-by-bit into a dividend shift register in a first order;
- outputting from the dividend shift register bit-by-bit in an order that is a reverse of the first order;
- entering at least one word of Bt bits of the quotient S bit-by-bit into a quotient shift register in a first order;
- and
- outputting from the quotient shift register bit-by-bit in an order that is a reverse of the first order.
A modular arithmetic coprocessor comprising:
- a division circuit to perform an integer division of a dividend A, encoded on a words of Bt bits, by a divider N, encoded on n words of Bt bits, to obtain a quotient S, encoded on α−n+1 words of Bt bits;
- said division circuit comprising at least one dividend shift register, to contain at least one word of the dividend A so that the word of the dividend A is entered in a first order and so as to output the word of the dividend A in an order that is the reverse of the first order.
A modular arithmetic coprocessor comprising;
- a division circuit to perform an integer division of a dividend A, encoded on α words of Bt bits, by a divider N, encoded on n words of Bt bits, to obtain a quotient S, encoded on α−n+1 words of Bt bits;
- said division circuit comprising at least one quotient shift register, to contain at least one word of the quotient S so that the word of the quotient S is entered in a first order and so as to output the word of the quotient S in an order that is the reverse of the first order.
A modular arithmetic coprocessor comprising:
- a division circuit to perform an integer division of a dividend A, encoded on α words of Bt bits, by a divider N, encoded on n words of Bt bits, to obtain a quotient S, encoded on α−n+1 words of Bt bits;
- said division circuit comprising
- at least one dividend shift register, to contain at least one word of the dividend A so that the word of the dividend A is entered in a first order and so as to output the word of the dividend A in an order that is the reverse of the first order, and
- at least one quotient shift register, to contain at least one word of the quotient S so that the word of the quotient S is entered in a first order and so as to output the word of the quotient S in an order that is the reverse of the first order.
Dependencies are inferred from the claim text.