Apparatus and method for circuit simulation which accounts for parasitic elements
AssigneeNEC Corporation
InventorHiroyoshi Kuge
Life of this patent
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Abstract
A simulation method of performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit, on the basis of a positional relationship between transistors, well contact interconnections, and sub-contact interconnections of the layout data. Parasitic resistances and parasitic capacitances in conductive regions between sub-terminals of the transistors are evaluated. A simulation apparatus for performing a circuit simulation by extracting resistances and capacitances from layout data of a circuit is also disclosed.
Claims4
A method of simulating a circuit, said method comprising:
- receiving layout data of said circuit, said layout data including well contact interconnections, and sub-contact interconnections of circuit elements in said circuit;
- and
- determining parasitic resistances and parasitic capacitances in conductive regions between sub-terminals of transistors in said circuit on the basis of positional relationships of said transistors, said well contact interconnections and said sub-contact interconnections in said circuit.
An apparatus for performing circuit simulation, said apparatus comprising:
- an input circuit which receives layout data of said circuit;
- and
- a processor which determines parasitic resistances and parasitic capacitances in conductive regions between sub-terminals of transistors on the basis of positional relationships of said transistors, said well contact interconnections and said sub-contact interconnections in said circuit.
Dependencies are inferred from the claim text.