Automatic adjustment for counting instrumentation

An information handling system for adjusting a counting rate of an instrumentation entity during simulation of a digital circuit design,

• wherein said digital circuit design including a design entity that is sequenced in accordance with a design cycle, wherein said design cycle is a multiple of a simulator cycle, said information handling system comprising:
• means for asserting a count event signal within said instrumentation entity in response to an occurence of an event within said design entity;
• means for generating a sampling signal having a cycle period equal to a period of said design cycle, wherein each cycle of said sampling signal includes a sampling pulse during which said sampling signal is asserted;
• means for comparing said sampling signal with said count event signal over said design cycle to determine whether both said sampling signal and said count event signal are asserted;
• and
• means for, in response to detecting that both said sampling signal and said count event signal are asserted, incrementing a counter, such that said counter is incremented in accordance with said design cycle rather than said simulator cycle.

A computer program product stored in signal bearing media for adjusting a counting rate of an instrumentation entity during simulation of a digital circuit design,

• wherein said digital circuit design including a design entity that is sequenced in accordance with a design cycle, wherein said design cycle is a multiple of a simulator cycle, said program product comprising:
• instruction means stored in signal bearing media for asserting a count event signal within said instrumentation entity in response to an occurrence of an event within said design entity;
• instruction means stored in signal bearing media for generating a sampling signal having a cycle period equal to a period of said design cycle, wherein each cycle of said sampling signal includes a sampling pulse during which said sampling signal is asserted;
• instruction means stored in signal bearing media for comparing said sampling signal with said count event signal over said design cycle to determine whether both said sampling signal and said count event signal are asserted;
• and
• instruction means stored in signal bearing media for, in response to detecting that both said sampling signal and said count event signal are asserted, incrementing a counter, such that said counter is incremented in accordance with said design cycle rather than said simulator cycle.

A counter for counting occurrences of an event that is detected within a simulation environment, wherein said simulation environment includes simulator latches that are sequenced in accordance with a simulator cycle, and wherein said event occurs in association with a design entity having design latches that are sequenced in accordance with a design cycle which is a multiple of said simulator cycle, said counter comprising:

• a first simulator latch that is sequenced in accordance with said simulator cycle, wherein said first simulator latch is a multi-bit storage device for recording said occurrences of said event;
• an incrementor having an input coupled to an output of said first simulator latch such that said incrementor produces an output incremented count value that is equal to a current count value stored within said first simulator latch incremented by one;
• selection means for applying said incremented count value to said input of said first simulator latch in response to receiving an asserted count select signal, and for applying said current count value to said input of said first simulator latch in response to not receiving said asserted count select signal;
• counting instrumentation means for providing a count event signal in response to detecting said count event;
• circuit means for providing a qualifier signal having a cycle equal to said design cycle;
• circuit means for detecting either a rising edge or a falling edge of said qualifier signal and producing a design cycle pulse in response thereto;
• and
• a logic gate for generating said asserted count select signal during a logic overlap of said count event signal with said design cycle pulse.