Optimizing hardware and software co-verification system

A machine readable medium comprising a plurality of instructions that, when executed, implement an optimizing hardware-software co-verification system, the hardware-software co-verification system including a bus interface model and/or a number of memory models, and a co-verification optimization manager for co-verification a hardware-software system having memory, wherein the co-verification of hardware and software is performed with a single coherent view of the memory of the hardware-software system such that selected portions of at least a first memory segment of the memory can be dynamically and/or statically configured/reconfigured for either unoptimized accesses or optimized accesses for all or selected portions of said one or more co-verification runs.

A machine implemented method for co-verifying a hardware-software system having memory, the method comprising:

• interleavingly verifying hardware and software for the hardware-software system for one or more co-verification runs;
• and
• periodically suspending said software verification, switching from said software verification to said hardware verification, and subsequently returning to said software verification during said one or more co-verification runs, such that verification time can be dynamically and/or statically configured/reconfigured to be optimized, and yet said hardware verification is nevertheless ensured to advance in a desired manner relative to said software verification.

In an optimizing hardware-software co-verification system, a method comprising:

• interleavingly verifying hardware and software for a hardware-software system having memory for one or more co-verification runs, and
• periodically suspend said software verification, switching from said software verification to said hardware verification, and subsequently return to said software verification during said one or more co-verification runs, such that verification time can be dynamically and/or statically configured/reconfigured to be optimized, and yet said hardware verification is nevertheless ensured to advance in a desired manner relative to said software verification.

A storage medium having stored therein a plurality of sequences of programming instructions to be executed by a processor, including first and second sequences of programming instructions to be executed to verify interleavingly hardware and software for a hardware-software system having memory for one or more co-verification runs, and third sequence of programming instructions to be executed to periodically suspend said software verification, switch from said software verification to said hardware verification, and subsequently return to said software verification during said one or more co-verification runs, such that verification time can be dynamically and/or statically configured/reconfigured to be optimized, and yet said hardware verification is nevertheless ensured to advance in a desired manner relative to said software verification.

In an optimizing hardware-software co-verification system, a method for co-verifying a hardware-software system having memory, the method comprising:

• interleavingly verifying hardware and software of the hardware and software system for one or more co-verification runs;
• concurrently facilitating by a co-verification optimization manager, a single coherent view of the memory of the hardware-software system by said verification of hardware and said verification of software during said one or more co-verification runs, such that selected portions of at least a first memory segment of the memory can be dynamically and/or statically configured/reconfigured for either unoptimized accesses or optimized accesses for all or selected portions of said one or more co-verification runs, wherein unoptimized accesses are performed through hardware verification, and optimized accesses are performed directly by said co-verification optimization manager, without hardware verification.

An apparatus comprising:

• one or more execution units for executing programing instructions;
• one or more storage medium having stored therein first and second sequences of programming instructions to be executed by the one or more execution units to interleavingly verify hardware and software of a hardware and software system having memory for one or more co-verification runs, and third sequence of programing instructions to be executed by the one or more execution units to concurrently facilitate a single coherent view of the memory of the hardware-software system by said verification of hardware and said verification of software during said one or more co-verification runs, such that selected portions of at least a first memory segment of the memory can be dynamically and/or statically configured/reconfigured for either unoptimized accesses or optimized accesses for all or selected portions of said one or more co-verification runs, wherein unoptimized accesses are performed through hardware verification, and optimized accesses are performed directly by said co-verification optimization manager, without hardware verification.

A storage medium having stored therein a plurality of programming instructions to be executed by a processor, including first and second sequences of programming instructions to be executed by the processor to interleavingly verify hardware and software of a hardware and software system having memory for one or more co-verification runs, and third sequence of programming instructions to be executed by the processor to concurrently facilitate a single coherent view of the memory of the hardware-software system by said verification of hardware and said verification of software during said one or more co-verification runs, such that selected portions of at least a first memory segment of the memory can be dynamically and/or statically configured/reconfigured for either unoptimized accesses or optimized accesses for all or selected portions of said one or more co-verification runs, wherein unoptimized accesses are performed through hardware verification, and optimized accesses are performed directly by said co-verification optimization manager, without hardware verification.