Full-duplex speakerphone circuit including a control interface

A fill-duplex communication circuit comprising:

• a signal path;
• a suppressor coupled to the signal path;
• a writable access port;
• a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a suppressor threshold field, the suppressor threshold field controlling the suppressor to set a speech detection threshold for disengaging suppression.

A full-duplex communication circuit comprising:

• a signal path;
• a suppressor coupled to the signal path;
• a writable access port;
• a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a double talk suppression disengage ramp rate field controlling the suppressor rate at which suppression attenuation returns to 0 dB on cessation of double talk.

A full-duplex communication circuit comprising:

• a receive signal path;
• a receive half-duplex controller coupled to the receive signal path;
• a transmit signal path;
• a transmit half-duplex controller coupled to the transmit signal path;
• and
• an echo canceller including an adaptive filter coupled to the transmit signal path and coupled to the receive signal path for accessing a first signal, determining a compensation signal from the first signal, and compensating a second signal using the compensating signal to form a compensated second signal having a loop gain reduction;
• a writable access port;
• a controller interface coupled to the access port and coupled to the half-duplex controller, the controller interface including a writable register having a field for controlling operation of the adaptive filter.

A full-duplex communication circuit comprising:

• a signal path;
• a programmable analog gain stage amplifier coupled to the signal path;
• a writable access port;
• a controller interface coupled to the access port and coupled to the programmable analog gain stage amplifier, the controller interface including a writable register, the writable register including a parameter for controlling the programmable analog gain stage amplifier.

A full-duplex communication circuit comprising:

• a receive signal path;
• a transmit signal path;
• and
• an echo canceller including an adaptive filter coupled to the transmit signal path and coupled to the receive signal path for accessing a first signal, determining a compensation signal from the first signal, and compensating a second signal using the compensating signal to form a compensated second signal having a loop gain reduction;
• a readable access port;
• a controller interface coupled to the readable access port and coupled to the half-duplex controller, the controller interface including a readable register having a field reporting a circuit status.