Fast response automatic gain control

A two-step automatic-gain-control (AGC) loop, for use with a receiver, comprising:

• an AGC amplifier, coupled to a receiving antenna, having an AGC gain, for amplifying a received signal;
• a received-signal-strength-indicator (RSSI) circuit, coupled to said AGC amplifier and responsive to an output signal from said AGC amplifier, for generating an RSSI signal proportional to a received-signal-power level of the received signal at a radio frequency (RF) stage of said receiver;
• an analog-to-digital converter, coupled to said RSSI circuit, for converting the RSSI signal to a digital RSSI signal;
• an RSSI-mapping circuit, coupled to said analog-to-digital converter and having an RSSI mapping table, responsive to the digital RSSI signal, for outputting, using the RSSI mapping table, a digital-AGC signal;
• an AGC register, coupled to said RSSI-mapping circuit, for storing the digital-AGC signal;
• a digital-to-analog converter, coupled to said AGC register and to said AGC amplifier, for converting the digital-AGC signal to an analog-AGC signal;
• said AGC amplifier, responsive to the analog-AGC signal, for adjusting the AGC gain;
• converter means, coupled to said AGC amplifier, for converting the output signal from said AGC amplifier to an in-phase component and a quadrature-phase component at a processing frequency;
• an in-phase analog-to-digital converter, coupled to said converter means, for converting the in-phase component to a digital in-phase signal;
• a quadrature-phase analog-to-digital converter, coupled to said converter means, for converting the quadrature-phase component to a digital quadrature-phase signal;
• an in-phase magnitude device, coupled to said in-phase analog-to-digital converter, for determining an in-phase magnitude of the digital in-phase signal;
• a quadrature-phase magnitude device, coupled to said quadrature-phase analog-to-digital converter, for determining a quadrature-phase magnitude of the digital quadrature-phase signal;
• an in-phase comparator, coupled to said in-phase magnitude device, for comparing the in-phase magnitude to a preset threshold, thereby generating an in-phase binary signal;
• a quadrature-phase comparator, coupled to said quadrature-phase magnitude device, for comparing the quadrature-phase magnitude to the preset threshold, thereby generating a quadrature-phase binary signal;
• a logic gate, coupled to said in-phase comparator and to said quadrature-phase comparator, for combining the in-phase binary signal and the quadrature-phase binary signal, to generate an error signal;
• an integrate-and-dump circuit, coupled to said logic gate and, responsive to the error signal indicating the in-phase magnitude and the quadrature-phase magnitude are high, for incrementing a counter of said integrate-and-dump circuit and, responsive to the error signal indicating the in-phase magnitude and the quadrature-phase magnitude are low, for decrementing the counter of the integrate-and-dump circuit and, responsive to the error signal indicating the in-phase magnitude and the quadrature-phase magnitude are different, for not changing the counter of said integrate-and-dump circuit, with an output of said integrate-and-dump circuit denoted an I&D signal;
• an AGC-convergence-rate multiplier, coupled to said integrate-and-dump circuit, for normalizing the I&D signal, thereby generating a normalized signal;
• said AGC register, responsive to the normalized signal, for updating the digital-AGC signal;
• said digital-to-analog converter for converting the updated digital-AGC signal, to an updated analog-AGC signal;
• and
• said AGC amplifier, responsive to the updated analog-AGC signal, for adjusting the AGC gain.