Single-type fabric card networks and method of implementing same
AssigneeLockheed Martin Corporation
InventorsSteven Allen Murphy, Donald Bruce Bennett, Brian Ralph Larson
Life of this patent
Estimating the term…
Abstract
An expandable network constructed from a plurality of identical network fabric cards which uses a plurality of selected row address bits to route connection paths between adjacent columns of interconnecting switches and a software algorithm for implementing a network of any whole number power of 2 rows or ports by assigning numbers of the network switches and attached nodes are described.
Claims10
A method for interconnecting switches in a network each of which interconnection switches have an equal number of input terminals of at least two input terminals and an equal number of output terminals of at least two output terminals, and are arranged into an even number of rows and an even number of columns of at least four rows and at least 2 columns on one or more cards, wherein the network is of the type which employs a selected plurality of row address bits to determine the routing of connection paths between adjacent columns of interconnection switches so that routing is made from the output terminals of the switches in a first column of switches to the input terminals of the interconnection switches in a second column of interconnection switches located immediately adjacent said first column of interconnection switches in accordance with unique identification numbers assigned to each of said interconnection switches comprising the steps of:
- (a) choosing the number of rows in the network;
- (b) choosing the number of columns per card;
- (c) choosing the number of row address bits that are to be routed;
- (d) calculating the minimum number of rows per card equal to 2n, where n=number of different row address bits routed per card;
- (e) determining if the minimum number of rows per card is to be employed or if instead an integer multiple of the minimum number of rows per card is to be used;
- (f) choosing which row address bits will be used to route circuit paths from the output terminals of each column of interconnection switches, except the output column, to the input terminals of each column of interconnection switches, except the input column;
- (g) sorting row address bits that are selected for use from the highest to the lowest number and associating sequentially numbered index bits with said row address bits such that each index bit is linked to the one of said row address bits that has the same relative position number with respect to the row address bit numbers as the associated index bit has with respect to the index bit numbers;
- (h) swapping the row address bit in the largest numbered physical row with the routed bit index bit associated with that physical row;
- (i) repeating step (h) for each of the row address bits;
- and
- (j) repeating steps (h) and (i) for each physical row number of the network.
A recursive multi-stage switching network comprising,
- (1) one or more fabric cards, each of which comprises interconnection switches, which have an equal number of input terminals of at least two input terminals and an equal number of output terminals of at least two output terminals and are arranged into an even number of rows of at least four and an even number of columns of at least two, wherein the network is of the type which employs a selected plurality of row address bits to determine the routing of connection paths between adjacent columns of interconnection switches so that routing is made from the output terminals of the interconnection switches in a first column of switches to the input terminals of interconnection switches in accordance with unique identification numbers assigned to each of said interconnection switches in which the interconnection path of each of said fabric cards in a network is identically wired regardless of the number of fabric cards employed in the network in accordance with the steps of:
- (a) choosing the number of rows in the network;
- (b) choosing the number of columns per card;
- (c) choosing the number of row address bits that are to be routed;
- (d) calculating the minimum number of rows per card equal to 2n, where n=number of bits routed per card;
- (e) determining if the minimum number of rows per card is to be employed, or if instead an integer multiple of the minimum number of rows per card is to be used;
- (f) choosing which row address bits will be used to route circuit paths from the output terminals of each column of interconnection switches, except the output column, to the input terminals of each column of interconnection switches, except the input column;
- (g) sorting row address bits that are selected for use from the highest to the lowest number and associating sequentially numbered index bits with said row address bits such that each index bit is linked to the one of said row address bits that has the same relative position number with respect to the row address bit numbers as the associated index bit has with respect to the index bit numbers;
- (h) swapping the row address bit in the largest number physical row with the routed bit index bit associated with that physical row;
- (i) repeating step (h) for each of the row address bits;
- and
- (j) repeating steps (h) and (i) for each physical row number of the network,
- (2) a column of additional input switches each having at least two input terminals and arranged into a number of rows equal to the number of rows of said interconnection switches and each associated with one of said rows of said interconnection switches, and
- (3) connection paths between said input switches and said fabric cards is made by using either the physical row numbers, or a permutation of said physical row numbers, of said input switches in accordance with step 5 of element (1) of this claim.
Dependencies are inferred from the claim text.