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US 6,212,128 B1Granted
Address transition detector in semiconductor memories
AssigneeSTMicroelectronics S.r.l.
InventorLuigi Pascucci
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AssigneeSTMicroelectronics S.r.l.
InventorLuigi Pascucci
Estimating the term…
An address transition detector in a semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to emit output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit comprising bistable memory circuits for storing the values of the address transition signals at each logical status changement of the adddress signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals. According to the present invention, said monostable circuit (123; 223; 303; 403) has breaking means (140; 240; 340; 440) of the feedback path (FB) in response to an enable signal (AE).
An address transition detector in semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to emit output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit including bistable memory circuits for storing the values of the address transition signals at each logical status changement of the address signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals, characterized in that said monostable circuit (123;
A method for detecting address transitions in semiconductor memories, which provides the use of a monostable circuit producing an output pulse signal in response to address signal changements, said monostable circuit requiring to send a complementary pair of address signals to a transition detector and storage circuit, which obtains an intermediate pulse signal from said complementary pair of address signals, said intermediate pulse signal being used along a feeback path to reset a memory circuit comprised in the transition detector and storage circuit, characterized in that it provides an enable signal (AE), which is apt to interrupt the feedback path (FB) through a pulse enable and synchronization circuit (440) so as to hinder resetting of the memory circuit comprised in the transition detector and storage circuit (403).
Dependencies are inferred from the claim text.