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US 6,212,127 B1Granted
Semiconductor device and timing control circuit
AssigneeHitachi, Ltd.
InventorsSeiji Funaba, Yoji Nishio, Yuichi Okuda, Yoshinobu Nakagome
Life of this patent
Estimating the term…
Abstract
Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
Claims24
A semiconductor device, comprising:
- a semiconductor chip including,
- a clock input circuit which inputs an external clock signal;
- a timing control circuit which inputs a first internal clock signal outputted from said clock input circuit to thereby output a second internal clock signal;
- and
- an internal circuit which inputs the second internal clock signal outputted from said timing control circuit;
- said timing control circuit including,
- a variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal;
- a dummy delay circuit which delays the second internal clock signal by a time associated with an operation delay time of a predetermined circuit on said semiconductor chip;
- a phase comparator which compares the phase of the first internal clock signal outputted from said clock input circuit with the phase of a signal outputted from said dummy delay circuit;
- a delay control circuit which controls a delay time of said variable delay circuit based on the result of comparison by said phase comparator;
- and
- speed control means which allows said dummy delay circuit, said phase comparator and said delay control circuit to operate at a frequency lower than that of said first internal clock signal.
9 more elements
A semiconductor device, comprising:
- a clock input circuit which inputs an external clock signal;
- a timing control circuit which inputs a first internal clock signal outputted from said clock input circuit to thereby output a second internal clock signal;
- and
- an internal circuit which inputs the second internal clock signal outputted from said timing control circuit;
- said timing control circuit including,
- a variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal;
- a delay circuit which delays an input signal with a signal propagation delay time corresponding to said variable delay circuit;
- a dummy delay circuit which delays a signal outputted from said delay circuit by a time associated with an operation delay time of a predetermined circuit;
- a phase determining circuit which determines the phase of a signal outputted from said dummy delay circuit, based on phase determining timing;
- a delay control circuit which controls a delay time of said variable delay circuit based on the result of determination by said phase determining circuit;
- and
- a timing signal generator which, every a plurality of cycles of the first internal clock signal outputted from said clock input circuit, controls said delay circuit so that a phase determining level signal is supplied to said delay circuit and supplies the phase determining timing for the phase determining level signal transmitted to said phase determining circuit to said phase determining circuit.
9 more elements
A semiconductor device, comprising:
- a semiconductor chip including,
- a clock input circuit which inputs an external clock signal;
- a timing control circuit which inputs a first internal clock signal outputted from said clock input circuit to thereby output a second internal clock signal;
- and
- an internal circuit which inputs the second internal clock signal outputted from said timing control circuit;
- said timing control circuit including,
- a first variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal;
- a second variable delay circuit having the same circuit configuration as said first variable delay circuit;
- a dummy delay circuit which reproduces an operation delay time of a predetermined circuit on said semiconductor chip and adds the operation delay time to a signal outputted from said second variable delay circuit;
- a phase determining circuit which determines the phase of a signal outputted from said dummy delay circuit, based on phase determining timing;
- a delay control circuit which feedback-controls delay times of said first variable delay circuit and said second variable delay circuit without discrimination, based on the result of determination by said phase determining circuit;
- a frequency-dividing circuit which outputs the first internal clock signal outputted from said clock input circuit as it is or divides the first internal clock signal and outputs the same therefrom;
- and
- a timing signal generator which, for every plural cycles of the clock signal outputted from said frequency-dividing circuit, supplies a phase determining level signal to said second variable delay circuit and supplies the phase determining timing for the phase determining level signal, which is fed back to said phase determining circuit, to said phase determining circuit.
11 more elements
A semiconductor device, comprising:
- a semiconductor chip including,
- a clock input circuit which inputs an external clock signal;
- a timing control circuit which inputs a first internal clock signal outputted from said clock input circuit to thereby output a second internal clock signal;
- and
- an internal circuit which inputs the second internal clock signal outputted from said timing control circuit;
- said timing control circuit including,
- a variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal;
- a delay circuit having a shift register configuration in which shift control terminals are successively coupled to a delay signal path of said variable delay circuit and an input signal is delayed with a signal propagation delay time equivalent to said variable delay circuit;
- a dummy delay circuit which reproduces an operation delay time of a predetermined circuit on said semiconductor chip and adds the operation delay time to a signal outputted from said delay circuit;
- a phase determining circuit which determines the phase of a signal outputted from said dummy delay circuit, based on phase determining timing;
- a delay control circuit which feedback-controls a delay time of said variable delay circuit, based on the result of determination by said phase determining circuit;
- a frequency-dividing circuit which outputs the first internal clock signal outputted from said clock input circuit as it is or divides the first internal clock signal and outputs the same therefrom;
- and
- a timing signal generator which, for every plural cycles of the clock signal outputted from said frequency-dividing circuit, controls said delay circuit so that a phase determining level signal is supplied to said delay circuit and supplies the phase determining timing for the phase determining level signal, which is fed back to said phase determining circuit, to said phase determining circuit.
11 more elements
A timing control circuit, comprising:
- a variable delay circuit which inputs a first internal clock signal to thereby output a second internal clock signal;
- a first delay circuit which delays an input signal with a signal propagation delay time equivalent to said variable delay circuit;
- a second delay circuit which outputs a signal outputted from said first delay circuit with a delay of a predetermined delay time;
- a phase determining circuit which determines the phase of a signal outputted from said second delay circuit, based on phase determining timing;
- a delay control circuit which controls the delay time of said variable circuit, based on the result of determination by said phase determining circuit;
- a timing signal generator which, for every plural cycles of the first internal clock signal, controls said first delay circuit so that a phase determining level signal is supplied to said first delay circuit, and supplies the phase determining timing for the phase determining level signal transmitted to said phase determining circuit, to said phase determining circuit;
- and
- a reset control circuit which sets said first and second delay circuits to an initial state respectively after the phase determining timing.
5 more elements
A timing control circuit, comprising:
- a first variable delay circuit which inputs a first internal clock signal to thereby output a second internal clock signal;
- a second variable delay circuit having the same circuit configuration as said first variable delay circuit;
- a dummy delay circuit which reproduces a predetermined delay time and gives the same to a signal outputted from said second variable delay circuit;
- a phase determining circuit which determines the phase of a signal outputted from said dummy delay circuit, based on phase determining timing;
- a delay control circuit which feedback-controls delay times of said first variable delay circuit and said second variable delay circuit without discrimination, based on the result of determination by said phase determining circuit;
- a timing signal generator which, for every plural cycles of the first internal clock signal, supplies a phase determining level signal to said second variable delay circuit and supplies the phase determining timing for the phase determining level signal, which is fed back to said phase determining circuit, to said phase determining circuit;
- and
- a reset control circuit which sets the outputs of said delay circuits and said dummy delay circuit to an initial level respectively after the phase determining timing.
5 more elements
A timing control circuit, comprising:
- a variable delay circuit which inputs a first internal clock signal to thereby output a second internal clock signal;
- a delay circuit having a shift register configuration in which shift control terminals are successively coupled to a delay signal path of said variable delay circuit and an input signal is delayed with a signal propagation delay time equivalent to said variable delay circuit;
- a dummy delay circuit which reproduces a predetermined delay time and gives the same to a signal outputted from said delay circuit;
- a phase determining circuit which determines the phase of a signal outputted from said dummy delay circuit, based on phase determining timing;
- a delay control circuit which feedback-controls a delay time of said variable delay circuit, based on the result of determination by said phase determining circuit;
- a timing signal generator which, for every plural cycles of the first internal clock signal, controls said delay circuit so that a phase determining level signal is supplied to said delay circuit and supplies the phase determining timing for the phase determining level signal, which is fed back to said phase determining circuit, to said phase determining circuit;
- and
- a reset control circuit which sets the outputs of said delay circuit and said dummy delay circuit to an initial level respectively after the phase determining timing.
5 more elements
A semiconductor device, comprising:
- a clock forming circuit formed over one semiconductor substrate, said clock forming circuit including,
- a first delay circuit which receives a first clock therein and thereby outputs a second clock obtained by delaying the first clock by a predetermined delay time;
- a first frequency-dividing circuit which outputs a third clock corresponding to a frequency-divided clock of the first clock in response to the first clock;
- a second frequency-dividing circuit which outputs a fourth clock corresponding to a frequency-divided clock of the second clock in response to the second clock;
- a second delay circuit which outputs a fifth clock corresponding to a delay clock of the fourth clock in response to the fourth clock;
- and
- a control circuit which compares the third clock with the fifth clock and outputs a signal for controlling the delay time of said first delay circuit based on the result of comparison to said first delay circuit.
4 more elements
A semiconductor device, comprising:
- a clock forming circuit including,
- a first delay circuit which receives a first clock having a first cycle and thereby outputs a second clock obtained by delaying the first clock;
- a second delay circuit which outputs a second signal obtained by delaying the first signal in response to the first signal;
- and
- a control circuit which determines the state of the second signal at the time that a third clock having a second cycle has changed from a first level to a second level, in response to the third clock and the second signal, and outputs a control signal based on the result of determination to said first delay circuit;
- and
- wherein said second delay circuit is set to an initial state in response to a fourth clock having the second cycle and formed on one semiconductor substrate.
4 more elements
Dependencies are inferred from the claim text.