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US 6,212,126 B1Granted
Semiconductor device including clock generation circuit capable of generating internal clock stably
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorWataru Sakamoto
Life of this patent
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Abstract
In a DLL circuit used as an internal clock generation circuit in a semiconductor device, a reset clock signal is output from one element of the delay circuit and applied to a pulse generator to trigger reset of a pulse signal.
Claims14
A semiconductor device comprising:
- a clock generation circuit generating an internal clock signal of said semiconductor device,
- said clock generation circuit including
- a first pulse generator generating a first pulse signal that is set in response to a first transition of a first reference clock signal that repeats the first transition from a first level to a second level and a second transition from the second level to the first level and reset in response to a predetermined level transition of a reset clock signal, and
- a delay circuit receiving an input clock signal according to said first pulse signal and providing said internal clock signal, said delay circuit including a plurality of delay stages connected in series to output said reset clock signal from a delay stage between the first delay stage and the last delay stage.
1 more element
A semiconductor device comprising:
- a clock generation circuit generating an internal clock signal of said semiconductor device,
- said clock generation circuit including
- a phase comparator circuit comparing phases of a first reference clock signal repeating a first transition from a first level to a second level and a second transition from the second level to the first level and said internal clock signal,
- a delay control circuit providing a delay control signal according to a comparison result generated from said phase comparator circuit,
- a first pulse generator generating a first pulse signal that is set in response to the first transition of said first reference clock signal, and that is reset at an elapse of a delay time controlled by said delay control signal, and
- a variable delay circuit receiving an input clock signal driven in response to said first pulse signal, and providing said internal clock signal delayed in response to said delay control signal.
3 more elements
Dependencies are inferred from the claim text.