Static RAM having word line driving circuitry shared by all the memory cells provided therein

A static random access memory comprising:

• a plurality of four-transistor memory cells arranged in an array, each of said memory cells comprising first and second field effect transistors respectively coupled to bit lines and controlled by word line potential, each of said memory cells further comprising third and fourth cross-coupled field effect transistors respectively coupled in series with said first and second field effect transistor and forming a circuit having two stable states;
• and
• a word line driving circuit shared by said plurality of four-transistor memory cells, said word line driving circuit reflecting a stable state potential change of each of said plurality of memory cells, and controlling an output voltage thereof which is applied to said plurality of memory cells in order to maintain the stable state potential in each of said plurality of memory cells;
• wherein said word line driving circuit further comprises:
• a monitor circuit comprising fifth and sixth field effect transistors which have opposite channel types and are coupled in series between a power source and ground, a potential at anode between said fifth and sixth transistors varying in response to said stable state potential change;
• and
• a word line voltage controller operatively coupled to said monitor circuit and said power source, said word line voltage controller responding to said potential at said node and controlling said output voltage of said word line driving circuit.