Memory system having flexible bus structure and method

A memory device comprising:

• a system bus interface to be coupled to a system bus which includes a tag bus and a data bus, with the system bus interface including a tag bus interface and a bi-directional data bus interface;
• an array of memory cells;
• a memory operation manager operably coupled to the system bus interface and to the array of memory cells, said memory operation manager being configured to carry out memory program and memory read operations on the array and
• comprising a command decoder and an address register block, with said memory operation manager operating to receive a memory address over the data bus interface, to receive at least part of a memory address command over the tag bus interface and to cause the received memory address to be loaded into the address register block in response to detection of the memory address command by the command decoder, with the memory operation manager operating to transfer data read from the array at the address stored in the address register block out of the memory device exclusively over the data bus interface during the memory read operation and operating to program data received by the memory device exclusively over the data bus interface into the array at the address stored in the address block during the memory program operation.

A memory device comprising:

• a system bus interface to be coupled to a system bus which includes a tag bus and a data bus, with the system bus interface including a tag bus interface and a bi-directional data bus interface;
• an array of memory cells;
• a memory operation manager operably coupled to the system bus interface and to the array of memory cells, said memory operation manager being configured to carry out memory program and memory read operations on the array and comprising a command decoder and an address register block, with said memory operation manager operating to receive a memory address over the data bus interface, to receive at least part of a memory address command over the tag bus interface and to cause the received memory address to be loaded into the address register block in response to detection of the memory address command by the command decoder, with the memory operation manager operating to transfer data read from the array at the address stored in the address register block out of the memory device exclusively over the data bus interface during the memory read operation and operating to program data received by the memory device exclusively over the data bus interface into the array at the address stored in the address block during the memory program operation,
• wherein the memory operation manager is further configured to control a direction that the data bus interface transfers data in response to control information received by way of the tag bus interface.

A memory device comprising:

• a system bus interface to be coupled to a system bus which includes a tag bus and a data bus, with the system bus interface including a tag bus interface and a bi-directional data bus interface;
• an array of memory cells;
• a memory operation manager operably coupled to the system bus interface and to the array of memory cells, said memory operation manager being configured to carry out memory program and memory read operations on the array and comprising a command decoder and an address register block, with said memory operation manager operating to receive a memory address over the data bus interface, to receive at least part of a memory address command over the tag bus interface and to cause the received memory address to be loaded into the address register block in response to detection of the memory address command by the command decoder, with the memory operation manager operating to transfer data read from the array at the address stored in the address register block out of the memory device exclusively over the data bus interface during the memory read operation and operating to program data received by the memory device exclusively over the data bus interface into the array at the address stored in the address block during the memory program operation,
• wherein the memory operation manager further comprises a program data register block and wherein the memory operation manager is further configured to transfer data present on the data bus interface to the program data register block in response to detection of a load program data command on the tag bus interface, with the memory operation manager operating to cause the data present in the program data register block to be programmed into the array.

A memory device comprising:

• a system bus interface to be coupled to a system bus which includes a data bus, with the system bus interface including a bi-directional data bus interface which is at least four bits wide;
• an array of memory cells;
• a memory operation manager operably coupled to the system bus interface and to the array of memory cells, said memory operation manager being configured to carry out memory read operations on the array, with said memory operation manager operating to receive a memory read address over the data bus interface, at least four address bits at a time, and to transfer data read from the array at the memory address over the data bus interface, at least four data bits at a time,
• wherein the memory operation manager is further configured to carry out memory program operations on the array, with said memory operation manager operating to receive a memory program address over the data bus interface, at least four address bits at a time, and to receive data to be programmed in the array at the memory program address over the data bus interface, at least four data bits at a time.

A memory device comprising:

• a system bus interface to be coupled to a system bus which includes a data bus and a tag bus, with the system bus including a bi-directional data bus which is at least four bits wide and a tag bus interface;
• an array of memory cells;
• a memory operation manager operably coupled to the system bus interface and to the array of memory cells, with said memory operation manager being configured to carry our memory read operations on the array and to carry out memory program operations on the array, with the memory operation manager including a command decoder operably coupled to the system bus interface and an address block which holds an array address used in the memory program and read operations, with the memory operation manager being configured to receive a first group of at least four address bits at one time on the data bus interface and to transfer the first group of address bits to the address block and to receive a second group of at least four address bits at one time on the data bus interface and to transfer the second group of address bits to the address block,
• wherein the tag bus interface is at least two bits wide and wherein the memory operations manager includes a command decoder operably coupled to the tag bus interface and wherein the first group of address bits are transferee to the address block in response to detection by the command decoder of a first address command on the tag bus interface.